GC4016 datasheet(11/83 Pages) TI

11 / 83 page

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August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

3+NZERO CLOCKS

SIB

Input

Sample taken

Data is sampled every

(NZERO+1) clocks thereafter

Figure 5. Zero Pad Synchronization

Zero padding lowers the effective decimation ratio. For

example, the minimum complex output decimation using a

single channel is normally 32. If the input data rate is 5 MSPS

and the system can clock the chip at 40 MHz, then the zero

pad function can be used to insert seven zeros between each

sample, padding the 5 MSPS input data rate up by a factor of

eight to 40 MSPS. The minimum decimation of 32 from the

40MHz rate results in an output rate of 1.25 MSPS, which is

an effective decimation of 4 relative to the original 5 MSPS

data.

A sync signal is used to synchronize the zero padding.

The ZPAD_SYNC control in address 19 selects the source of

the sync signal. The sync signal can be used to identify when

the chip will sample the input data. Figure 5 shows the timing

when SIB (ZPAD_SYNC=3) is selected as the sync source.

Zero padding can be used to synchronize extracting

data from a TDM bus. By adjusting the timing of SIB as

shown in Figure 5, the user can choose which sample to take

from the TDM bus.

The zero pad function has a gain equal to:

ZPAD_GAIN =1/(1+NZERO).

3.3.2 The Numerically Controlled Oscillator

(NCO)

The tuning frequency of each down converter is

specified as a 32 bit word and the phase offset is specified as

a 16 bit word. The NCOs can be synchronized with NCOs on

other chips. This allows multiple down converter outputs to

be coherently combined, each with a unique phase and

amplitude. A block diagram of the NCO circuit is shown in

Figure 6.

The tuning frequency is set to FREQ according to the

formula FREQ = 232F/FCK, where F is the desired tuning

frequency and FCK is the chip’s clock rate. The 16 bit phase

offset setting is PHASE = 216P/2

π, where P is the desired

phase in radians ranging between 0 and 2

π.

Note that a positive tuning frequency should be used to

downconvert the signal. A negative tuning frequency can be

used to upconvert the negative (spectrally flipped) image of

the desired signal. FREQ and PHASE are set in addresses

16 through 21 of each channel frequency pages.

The NCO’s frequency, phase and accumulator can be

initialized and synchronized with other channels using the

FREQ_SYNC, PHASE_SYNC, and NCO_SYNC controls in

addresses 17 and 18 of the channel control pages. The

FREQ_SYNC and PHASE_SYNC controls determine when

new frequency and phase settings become active. Normally

these are set to “always” so that they take effect immediately,

but can be used to synchronize frequency hopping or beam

forming systems. The NCO_SYNC control is usually set to

never, but can be used to synchronize the LOs of multiple

channels.

The NCO’s spur level is reduced to below -113 dB

through the use of phase dithering. The spectrums in Figure

7 show the NCO spurs for a worst case tuning frequency

before and after dithering has been turned on. Notice that the

spur level decreases from -105 dB to -116 dB. Dithering is

turned on or off using the DITHER_SYNC control in address

18.

The worst case NCO spurs at -113 to -116dB, such as

the one shown in Figure 7(b), are due to a few frequencies

that are related to the sampling frequency by multiples of

FCK/96 and FCK/124. In these cases the rounding errors in

32 BITS

20 BITS

32 BITS

FREQ

SINE/COSINE

OUT

23 MSBs

5 BITS

18 MSBs

DITHER

GENERATOR

PHASE

16 BITS

SINE/COSINE

LOOKUP

TABLE

Figure 6. NCO Circuit

GC4016 Datasheet(PDF) 11 Page - Texas Instruments

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