GC4016 datasheet(13/83 Pages) TI

13 / 83 page

- 8 -

August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

UPPER

24 BITS

DATA

OUT

CLOCKED AT FULL RATE

CLOCKED AT 1/N RATE

24 BITS

20 BITS

Figure 9. Five Stage CIC Decimate by N Filter

The CIC filter has a gain equal to N5 which must be

compensated for in the “CIC_SCALE” circuit shown in Figure

The

CIC_SCALE

circuit

has

gain

equal

2(SHIFT+SCALE+6*BIG_SCALE-62), where SCALE ranges from 0

to 5 and BIG_SCALE ranges from 0 to 7. The range of SHIFT

is 4-7 if MIX20B is enabled and is 0-7 if MIX20B is disabled.

The overall gain of the CIC circuit is equal to:

The user must select values for SHIFT, SCALE and

BIG_SCALE (addresses 16 and 23 of each channel control

page) such that CIC_GAIN (including ZPAD_GAIN if

blanking is used) is less than one, i.e., SHIFT, SCALE and

BIG_SCALE must be selected such that:

Overflows due to improper gain settings will go

undetected if this relationship is violated. For example, if N is

equal to 8 and SHIFT=4, then this restriction means that

BIG_SCALE and SCALE should be less than or equal to 7

and 1 respectively. The SHIFT, BIG_SCALE and SCALE

settings are independent for each channel. See Section 3.7

for a description of the channel’s overall gain.

3.3.4 Coarse Channel Gain

The gain of each channel can be boosted up to 42 dB by

shifting the output of the CIC filter up by 0 to 7 bits prior to

rounding

bits.

The

coarse

gain

is:

, where COARSE ranges from

0 to 7. COARSE is set in address 25 of each channel control

page. Overflows in the coarse gain circuit are saturated to

plus or minus full scale. The coarse gain is used to increase

the gain of an individual signal after the input bandwidth of

the downconverter has been reduced by a factor of N in the

CIC filter. If the signal power across the input bandwidth is

relatively flat, as is the case in most frequency division

multiplexed (FDM) systems, then one would want to boost

the signal power out of the CIC filter by a factor of

. Each channel can be given its own

coarse gain setting. See Section 3.7 for a description of the

channel’s overall gain.

3.3.5 The First Decimate By Two Filter

(CFIR)

The CIC/Coarse gain outputs are filtered by two stages

of filtering. The first stage is a 21 tap decimate by 2 filter with

programmable 16 bit coefficients. Since this filter decimates

by two, a stopband must be created in that portion of the

spectrum that would alias into the signal of interest. This filter

has very lax transition band specifications so 21 taps is

sufficient to both provide the required anti-aliasing stopband,

and to provide compensation for the droop in the CIC filter’s

passband. The CFIR is also used, in some cases, to provide

additional stopband rejection for the second stage PFIR filter.

Figure

illustrates

the

passband

and

stopband

requirements of the filter. FCFIR is the input sample rate to the

CFIR filter. FCFIR/4 is the output sample rate of the channel

before resampling.

The user downloaded filter coefficients are 16 bit 2’s

complement numbers. Unity gain will be achieved through

the filter if the sum of the 21 coefficients is equal to 65536. If

the sum is not 65536, then CFIR will introduce a gain equal

to:

, where CFIR_SUM is the sum of

the 21 coefficients. Coefficient sets for a variety of standards

in cellular and cable modem applications are given in Section

7. The output of CFIR is rounded to 20 bits (using the

round-to-even algorithm). Overflows are detected and hard

limited. Overflows can be directed to the channel overflow

detection block.

The 21 coefficients are identified as coefficients h0

through h20, where h10 is the center tap. The coefficients are

assumed to be symmetric, so only the first 11 coefficients (h0

through h10) are loaded into the chip. A non-symmetric mode

(NO_SYM_CFIR in address 25) allows the user to download

an 11 tap non-symmetric filter as taps h0 through h10. The

newest sample is multiplied by h0 and the oldest is multiplied

by h10. NOTE: Filters normally multiply h0 by the oldest data,

hence one may wish to reverse the tap order in the

non-symmetric mode.

CFIR has a programmable delay of one CFIR input

sample. This delay is used in a multichannel mode to alter

CIC_GAIN

2 SHIFT +SCALE

BIG_SCALE

–

(

)

SHIFT

SCALE6

BIG_SCALE

(

) ≤

5log

–

log

2(NZERO+1)

(

)

COARSE_GAIN

COARSE

COARSE_GAIN

CFIR_GAIN

CFIR_SUM

65536

-----------------------------

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