GC4016 datasheet(24/83 Pages) TI

24 / 83 page

- 19 -

August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

In the complex to real conversion modes (see Section

3.3.7), the real output is available in the Q portion of the

registers and the I portion is invalid. The REAL_ONLY

control has no effect upon the microprocessor mode.

Tables 4, 5 and 6 assume the block size control

(BLOCK_SIZE in address 20) is set to four samples. If the

block size is two and OUTPUT_ORDER is 0, then page 97 is

unused. If the block size is one and OUTPUT_ORDER is 0,

then only addresses 16 through 23 of page 96 are used.

3.8.2 Wide Word Microprocessor Mode

The wide word microprocessor mode is selected by

setting OUTPUT_MODE=0 and by enabling the parallel

output port (EN_P0=EN_P1=EN_P2=EN_P3=EN_PAR=1 in

address 16). The wide word microprocessor mode allows the

user to read 32 bit words, rather than bytes. The 8 bit

microprocessor port is augmented with the 24 bit parallel port

to provide the 32 bit interface. The bit mapping into the 32 bit

port is shown below.

The channel outputs are read using addresses 16, 20,

24, and 28 of pages 96 and 97. The channel ordering is the

same as described in Section 3.8.1 above and shown in

Tables 4, 5 and 6.

The upper 24 bits of the wide word microprocessor port

are read only bits. The port and has the same control and

timing characteristics as shown in Figures 2 and 3 for the

normal microprocessor port.

3.8.3 Synchronous Serial Outputs

The

serial

mode

selected

setting

OUTPUT_MODE=1, MASTER=1 and enabling the serial

output pins (EN_SCK=EN_SFS=EN_P0,1,2,3=1 in address

16). The chip provides a bit serial clock (SCK), a frame strobe

(SFS) and four data bit lines (SOUT A,B,C and D) to output

the data in a serial format. The I and Q parts of complex

outputs are always multiplexed onto the same bit-serial pin.

The I-part is output first, MSB to LSB, followed by the Q-part.

In the real mode (REAL_ONLY=1), only the Q word per

channel is output. The REAL_ONLY mode is used with the

complex to real conversion mode of the PFIR.

The serial clock is the input clock (CK) divided by 1-16

(SCK_RATE control in address 21). For even divisions, the

serial clock changes on the rising edge of CK. The serial

clock has a 50% duty cycle for all divisions. The polarity of

the serial clock is programmable (which allows output data to

be sampled on the rising or falling edge of SCK).

The serial output word size is programmable to be

12,16,20,24,28, or 32 bits per word (BITS_PER_WORD

control in address 20). Note that the maximum word size out

of the resampler is 24 bits so for output word sizes of 28 or

32 bits the lower bits are always zero. For complex data

outputs, pairs of words, each being 12 to 32 bits, are output.

Synchronous channel outputs can be transmitted as one

channel per serial output on four separate bit-serial output

pins

(SOUTA,

SOUTB,

SOUTC,

and

SOUTD),

multiplexed as two channels per pin onto two output pins

(SOUTA and SOUTB), or multiplexed as all four channels on

the

same

(SOUTA)

specified

the

OUTPUT_ORDER and NSERIAL control bits in address 21.

The four channel, each on their own serial pin, mode uses

NSERIAL=3 and OUTPUT_ORDER=2. The two channels

per pin mode uses NSERIAL=1 and OUTPUT_ORDER=1.

The four channels on a single pin mode uses NSERIAL=0

and OUTPUT_ORDER=0.

The serial streams SOUTA, SOUTB, SOUTC and

SOUTD are normally output on pins P0, P1, P2 and P3,

respectfully. If required, the SMUX_0, SMUX_1, SMUX_2

and SMUX_3 controls in address 22 can be used to select

which stream is output on which of these pins.

For

synchronous

channels

the

FIFO

block

size

(BLOCK_SIZE) should be set to match the number of active

channels. If four channels are active, then BLOCK_SIZE

should be set to 3. If two channels are active, then

BLOCK_SIZE should be set to 1. If only one channel is

active, then BLOCK_SIZE should be set to 0.

The outputs are output in frames. Output frames start

when the previous frame has completed AND a new data

block is ready in the FIFO (See BLOCK_SIZE above). The

minimum output frame length can be programmed to be 1 to

words

(up

complex

samples)

using

the

FRAME_LENGTH control in address 19. Longer frame sizes

can be used to time division multiplex (TDM) channels from

multiple chips onto a signal serial bus or to smooth data flow

when resampling.

The number of words output on each serial pin during a

frame can be programmed to be 1 to 8 words (1 to 4 complex

P23

LSB

MSB

CONTROL PORT

PARALLEL PORT

32 BIT Wide Word PORT

(reads back zero)

(contains the 24 bit output data)

Figure 14. Wide Word Microprocessor Port

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