GC4016 datasheet(12/83 Pages) TI

12 / 83 page

- 7 -

August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

a) Worst case spectrum without dither

b) Spectrum with dither (tuned to same frequency)

-105 dB

-116 dB

FREQ=5/24 FS

Figure 7. Example NCO Spurs

-121 dB

-107 dB

a) Plot without dither or phase initialization

b) Plot with dither and phase initialization

Figure 8. NCO Peak Spur Plot

the sine/cosine lookup table repeat in a regular fashion,

thereby concentrating the error power into a single

frequency, rather than spreading it across the spectrum.

These worst case spurs can be eliminated by selecting an

initial phase that minimizes the errors or by changing the

tuning frequency by a small amount (50 Hz). Setting the

initial phase to 4 for multiples of FCK/96 or FCK/124 (and to 0

for other frequencies) will result in spurs below -115 for all

frequencies.

Figure 8 shows the maximum spur levels as the tuning

frequency is scanned over a portion of the frequency range

with the peak hold function of the spectrum analyzer turned

on. Notice that the peak spur level is -107 dB before dithering

and is -121 dB after dithering has been turned on and the

phase initialization described above has been used.

The output of the mixer may be rounded to 16 or 20 bits.

Twenty bit rounding (MIX20B is set in address 23) is normally

used with the 14 or 16 bit input modes. Sixteen bit rounding

(MIX20B disabled) is normally used with the floating point, 12

bit input modes. Sixteen bit rounding is also required to

achieve a CIC gain of less than or equal to unity when the

CIC decimation is greater than 3104. See Table 1.

3.3.3 Five Stage CIC Filter

The mixer outputs are decimated by a factor of N in a

five stage CIC filter, where N is any integer between 8 and

4096 (between 4 and 2048 for SPLITIQ mode). The value of

N is programmed independently for each channel in

addresses 21 and 22 of each channel control page. The

programmable decimation allows the chip’s usable output

bandwidth to range from less than 4 kHz to over 3 MHz when

the input rate is 100 MHz. Wider output bandwidths are

obtainable by using multiple channels (see Section 3.4). A

block diagram of the CIC filter is shown in Figure 9.

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