AD9175 datasheet(149/150 Pages) AD

149 / 150 page

Data Sheet

AD9175

Rev. A | Page 149 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

[5:0]

PLL_CTRL2

DAC PLL optimization control.

0x1C

R/W

0x799

DACPLL_CTRL7

[7:6]

ADC_CLK_DIVIDER

ADC clock output divider.

0x0

R/W

Divide by 1.

Divide by 2.

Divide by 3.

Divide by 4.

[5:0]

N_DIVIDER

Programmable divide by N value from

2 to 50. N_DIVIDER = (DAC frequency ×

M_DIVIDER)/(8 × reference clock frequency).

0x8

R/W

0x7A0

DACPLL_CTRL9

[7:6]

RESERVED

Reserved.

0x2

R/W

D_EN_VAR_FINE_

PRE

DAC PLL control.

0x0

R/W

[4:3]

RESERVED

Reserved.

0x2

R/W

D_EN_VAR_

COARSE_PRE

DAC PLL control.

0x0

R/W

[1:0]

RESERVED

Reserved.

0x0

R/W

0x7A2

DACPLL_CTRL10

RESERVED

Reserved.

0x0

[6:5]

D_REGULATOR_

CAL_WAIT

DAC PLL optimization control.

0x1

R/W

[4:3]

D_VCO_CAL_WAIT

DAC PLL optimization control.

0x2

R/W

[2:1]

D_VCO_CAL_

CYCLES

DAC PLL optimization control.

0x2

R/W

RESERVED

Reserved.

0x1

R/W

0x7B5

PLL_STATUS

[7:1]

RESERVED

Reserved.

0x0

PLL_LOCK

DAC PLL lock status.

0x0

AD9175 Datasheet(PDF) 149 Page - Analog Devices

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