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C161 Datasheet(PDF) 120 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 120 Page - Infineon Technologies AG |
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120 / 400 page  &3, &ORFN*HQHUDWLRQ User’s Manual 6-4 1999-08 6.2 Frequency Control The CPU clock is generated from the oscillator clock in either of two software selectable ways: The basic clock is the standard operating clock for the C161PI and is required to deliver the intended maximum performance. The configuration via PORT0 (CLKCFG) after a long hardware reset determines one of three possible basic clock generation modes: • Direct Drive: the oscillator clock is directly fed to the controller hardware. • Prescaler: the oscillator clock is divided by 2 to achieve a 50% duty cycle. • PLL: the oscillator clock is multiplied by a configurable factor of F = 1.5...5. The Slow Down clock is the oscillator clock divided by a programmable factor of 1...32 (additional 2:1 divider in prescaler mode). This alternate possibility runs the C161PI at a lower frequency (depending on the programmed slow down factor) and thus greatly reduces its power consumption. Figure 6-4 Frequency Control Paths The internal operation of the C161PI is controlled by the internal CPU clock f CPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations (see figure below). Configuration Software PLL SDD 2:1 Oscillator clock CPU clock f CPU f OSC OWD |
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