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C161 Datasheet(PDF) 122 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 122 Page - Infineon Technologies AG |
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122 / 400 page  &3, &ORFN*HQHUDWLRQ User’s Manual 6-6 1999-08 Direct Drive When direct drive is configured (CLKCFG=’011’) the C161PI’s clock system is directly fed from the external clock input, i.e. I CPU = IOSC. This allows operation of the C161PI with a reasonably small fundamental mode crystal. The specified minimum values for the CPU clock phases (TCLs) must be respected. Therefore the maximum input clock frequency depends on the clock signal’s duty cycle. Prescaler Operation When prescaler operation is configured (CLKCFG=’001’) the C161PI’s input clock is divided by 2 to generate then CPU clock signal, i.e. I CPU = IOSC/2. This requires the oscillator (or input clock) to run on 2 times the intended operating frequency but guarantees a 50% duty cycle for the internal clock system independent of the input clock signal’s waveform. PLL Operation When PLL operation is configured (via CLKCFG) the C161PI’s input clock is fed to the on-chip phase locked loop circuit which multiplies its frequency by a factor of F = 1.5...5 (selectable via CLKCFG, see table below) and generates a CPU clock signal with 50% duty cycle, i.e. I CPU = I OSC*F. The on-chip PLL circuit allows operation of the C161PI on a low frequency external clock while still providing maximum performance. The PLL also provides fail safe mechanisms which allow the detection of frequency deviations and the execution of emergency actions in case of an external clock failure. When the PLL detects a missing input clock signal it generates an interrupt request. This warning interrupt indicates that the PLL frequency is no more locked, i.e. no more stable. This occurs when the input clock is unstable and especially when the input clock fails completely, e.g. due to a broken crystal. In this case the synchronization mechanism will reduce the PLL output frequency down to the PLL’s base frequency (2...5 MHz). The base frequency is still generated and allows the CPU to execute emergency actions in case of a loss of the external clock. On power-up the PLL provides a stable clock signal within ca. 1 ms after 9 DD has reached the specified valid range, even if there is no external clock signal (in this case the PLL will run on its base frequency of 2...5 MHz). The PLL starts synchronizing with the external clock signal as soon as it is available. Within ca. 1 ms after stable oscillations of the external clock within the specified frequency range the PLL will be synchronous with this clock at a frequency of F * I OSC, i.e. the PLL locks to the external clock. When PLL operation is selected the CPU clock is a selectable multiple of the oscillator frequency, i.e. the input frequency. |
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