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C161 Datasheet(PDF) 208 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 208 Page - Infineon Technologies AG |
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208 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-16 1999-08 Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. For counter operation, pin TxIN must be configured as input, i.e. the respective direction control bit must be ‘0’. The maximum input frequency which is allowed in counter mode is f CPU/16. To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized, its level should be held for at least 8 f CPU cycles before it changes. Table 10-6 GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection T2I / T4I Triggering Edge for Counter Increment / Decrement X 0 0 None. Counter Tx is disabled 0 0 1 Positive transition (rising edge) on TxIN 0 1 0 Negative transition (falling edge) on TxIN 0 1 1 Any transition (rising or falling edge) on TxIN 1 0 1 Positive transition (rising edge) of output toggle latch T3OTL 1 1 0 Negative transition (falling edge) of output toggle latch T3OTL 1 1 1 Any transition (rising or falling edge) of output toggle latch T3OTL |
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