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C161 Datasheet(PDF) 205 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 205 Page - Infineon Technologies AG |
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205 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-13 1999-08 10.1.2 GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer, gated timer, counter, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3. In addition to these 4 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. The individual configuration for timers T2 and T4 is determined by their bitaddressable control registers T2CON and T4CON, which are both organized identically. Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers. T2CON Timer 2 Control Register SFR (FF40 H/A0H) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - --- -- - T2 UDE T2 UD T2R T2M T2I - - - - - - - rw rw rw rw rw T4CON Timer 4 Control Register SFR (FF44 H/A2H) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - --- -- - T4 UDE T4 UD T4R T4M T4I - - - - - - - rw rw rw rw rw Bit Function TxI Timer x Input Selection Depends on the Operating Mode, see respective sections. TxM Timer x Mode Control (Basic Operating Mode) 000: Timer Mode 001: Counter Mode 010: Gated Timer with Gate active low 011: Gated Timer with Gate active high 100: Reload Mode 101: Capture Mode 110: Incremental Interface Mode 111: Reserved. Do not use this combination. TxR Timer x Run Bit 0: Timer / Counter x stops 1: Timer / Counter x runs |
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