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C161 Datasheet(PDF) 202 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 202 Page - Infineon Technologies AG |
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202 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-10 1999-08 The incremental encoder can be connected directly to the C161PI without external interface logic. In a standard system, however, comparators will be employed to convert the encoder’s differential outputs (e.g. A, A) to digital signals (e.g. A). This greatly increases noise immunity. Note: The third encoder output Top0, which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a reset of timer T3 (e.g. via PEC transfer from ZEROS). Figure 10-7 Connection of the Encoder to the C161PI For incremental interface operation the following conditions must be met: • Bitfield T3M must be ’110 B’. • Both pins T3IN and T3EUD must be configured as input, i.e. the respective direction control bits must be ‘0’. • Bit T3UDE must be ’1’ to enable automatic direction control. Table 10-4 GPT1 Core Timer T3 (Incremental Interface Mode) Input Edge Selection T3I Triggering Edge for Counter Increment / Decrement 0 0 0 None. Counter T3 stops. 0 0 1 Any transition (rising or falling edge) on T3IN. 0 1 0 Any transition (rising or falling edge) on T3EUD. 0 1 1 Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD). 1 X X Reserved. Do not use this combination A A B B T0 T0 A B T0 Signal conditioning T3input T3input Interrupt |
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