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C161 Datasheet(PDF) 200 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 200 Page - Infineon Technologies AG |
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200 / 400 page ![]() &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-8 1999-08 Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘001 B’. In counter mode timer T3 is clocked by a transition at the external input pin T3IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this pin. Bit field T3I in control register T3CON selects the triggering transition (see table below). Figure 10-5 Block Diagram of Core Timer T3 in Counter Mode Table 10-3 GPT1 Core Timer T3 (Counter Mode) Input Edge Selection T3I Triggering Edge for Counter Increment / Decrement 0 0 0 None. Counter T3 is disabled 0 0 1 Positive transition (rising edge) on T3IN 0 1 0 Negative transition (falling edge) on T3IN 0 1 1 Any transition (rising or falling edge) on T3IN 1 X X Reserved. Do not use this combination Core Timer Tx TxR XOR 0 MUX 1 Up/ Down TxEUD TxUDE MCB02030 TxUD Txl TxIN Edge Select TxOTL Interrupt Request TxOE TxOUT T3IN = P3.6 T3EUD = P3.4 T3OUT = P3.3 x = 3 |
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