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C161 Datasheet(PDF) 201 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 201 Page - Infineon Technologies AG |
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201 / 400 page  &3, 7KH*HQHUDO 3XUSRVH 7LPHU8QLWV User’s Manual 10-9 1999-08 For counter operation, pin T3IN must be configured as input, i.e. the respective direction control bit DPx.y must be ‘0’. The maximum input frequency which is allowed in counter mode is f CPU/16. To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized, its level should be held high or low for at least 8 f CPU cycles before it changes. Timer 3 in Incremental Interface Mode Incremental Interface mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘110 B’. In incremental interface mode the two inputs associated with timer T3 (T3IN, T3EUD) are used to interface to an incremental encoder. T3 is clocked by each transition on one or both of the external input pins which gives 2-fold or 4-fold resolution of the encoder input. Figure 10-6 Block Diagram of Core Timer T3 in Incremental Interface Mode Bitfield T3I in control register T3CON selects the triggering transitions (see table below). In this mode the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. So T3 is modified automatically according to the speed and the direction of the incremental encoder and its contents therefore always represent the encoder’s current position. Edge Select Timer T3 XOR 0 MUX 1 T3EUD T3UDE MCB04000B T3UD T3l T3IN T3OTL Interrupt Request T3OUT Phase Detect T3OE T3R |
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