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DS3172 Datasheet(PDF) 129 Page - Dallas Semiconductor

Part # DS3172
Description  Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
PDF  232 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3172 Datasheet(HTML) 129 Page - Dallas Semiconductor

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Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this
RST bit), on all of the ports, will be reset to their default state. This bit must be set high for a minimum of 100ns.
See the Reset and Power-Down section in Section 10.3.
0 = Normal operation
1 = Force all internal registers to their default values
Register Name:
GL.CR2
Register Description:
Global Control Register 2
Register Address:
004h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
G8KRS2
G8KRS1
G8KRS0
G8K0S
G8KIS
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
CLAD3
CLAD2
CLAD1
CLAD0
Default
0
0
0
0
0
0
0
0
Bits 12 to 10: Global 8KHz Reference Source [2:0] (G8KRS[2:0]). These bits determine the source for the
internally generated 8 kHz reference as well as the internal one second reference, which is derived from the Global
8 kHz reference. The source is selected from one of the CLAD clocks or from one of the port 8KREF clock sources.
These bits are ignored when the G8KIS bit = 1.
Table 10-12. Global 8 kHz Reference Source Table
GL.CR2.
G8KIS
GL.CR2.
G8KRS[2:0]
Source
0
000
None, the 8KHZ divider is disabled.
0
001
Derived from CLAD DS3 clock output or CLKA pin if CLAD is
disabled. (Note: CLAD is disabled after reset)
0
010
Derived from CLAD E3 clock output or CLKB pin if CLAD is
disabled
0
011
Derived from CLAD STS-1 clock output or CLKC pin if CLAD
is disabled
0
100
Port 1 8KREF source selected by P8KRS[1:0]
0
101
Port 2 8KREF source selected by P8KRS[1:0]
0
110
Port 3 8KREF source selected by P8KRS[1:0]
0
111
Port 4 8KREF source selected by P8KRS[1:0]
1
XXX
GPIO4 pin
Bit 9: Global 8KHz Reference Output Select (G8KOS). This bit determines whether GPIO2 pin is used for the
global 8KREFO output signal, or is used as specified by GL.GIOCR.GPIO2S[1:0].
0 = GPIO2 pin mode selected by GL.GIOCR.GPIO2S[1:0]
1 = GPIO2 is the global 8KREFO output signal selected by GL.CR2.8KRS[2:0]
Bit 8: Global 8KHz Reference Input Select (G8KIS). This bit determines whether GPIO4 pin is used for the global
8KREFI input signal, or is used as specified by GL.GIOCR.GPIO4S[1:0]. G8KREFI signal will be low if not
selected. Global 8KREF pin signal will be low if not selected.
0 = GPIO4 pin mode selected by GL.GIOCR.GPIO4S[1:0]
1 = GPIO4 is the global 8KREFI input signal for one second timer and ports to use
Bits 3 to 0: CLAD IO Mode [3:0] (CLAD[3:0]). These bits control the CLAD clock IO pins CLKA, CLKB and CLKC.
Note: These bits control which clock is used to recover the RX Clock from the line in the LIU.



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