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DS3172 Datasheet(PDF) 213 Page - Dallas Semiconductor |
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DS3172 Datasheet(HTML) 213 Page - Dallas Semiconductor |
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213 / 232 page  DS3171/DS3172/DS3173/DS3174 213 of 232 Figure 14-2. DS3173 Pin Assignments—400-Lead BGA 1 2 3 4 5 6 7 8 9 101112 1314151617181920 A VSS VDD RPOS1 VDD_RX3 RXN3 TXN3 TSOFO1 TLCLK1 RCLKO3 RLCLK3 TCLKO3 TCLKI3 RNEG3 VSS B MODE ROHSOF 1 RNEG1 TCLKI1 RXP3 TXP3 TSOFI1 RLCLK1 RSER3 RSOFO3 TNEG3 RPOS3 RST* VDD C GPIO[5] GPIO[6] A[10] TPOS1 VDD_JA3 TOHSOF 1 TOHCLK1 TLCLK3 TSOFO3 TSER3 TPOS3 D VDD_RX1 A[5] A[9] TNEG1 ROHCLK 1 TCLKO1 TOH1 RCLKO1 ROH1 TOH3 TSOFI3 ROHSOF 3 E A[1] A[4] A[8] JTRST* TOHEN1 TSER1 VDD_TX3 RSOFO1 RSER1 ROH3 TOHCLK3 TOHSOF 3 ROHCLK 3 TOHEN3 F RXN1 RXP1 JTCLK JTMS GPIO[1] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD G VDD_JA1 A[3] A[7] JTDO GPIO[2] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD H A[0] A[2] A[6] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD J TXN1 TXP1 JTDI VDD_TX1 D[15] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS K CLKA RDY* RD* WR* VDD_CLA D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS L CLKB CLKC CS* INT* WIDTH VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS M TXN2 TXP2 TEST* VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N VDD_TX2 ALE D[6] D[11] VDD_JA2 VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD P D[0] D[2] D[7] D[12] GPIO[4] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD R RXN2 RXP2 HIZ* D[13] GPIO[3] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD T VDD_RX2 D[3] D[8] D[14] TOHEN2 TSER2 RSOFO2 RSER2 U D[1] D[4] D[9] TNEG2 ROHCLK 2 TCLKO2 TOH2 RCLKO2 ROH2 V GPIO[7] GPIO[8] D[10] TPOS2 TOHSOF 2 TOHCLK2 W VDD D[5] RNEG2 TCLKI2 TSOFI2 RLCLK2 Y VSS ROHSOF 2 RPOS2 TSOFO2 TLCLK2 VDD VSS Note: Green indicates VSS; red indicates VDD; blank cells indicate No Connect balls. Figure 14-3. DS3172 Pin Assignments—400-Lead BGA 1 2 3 4 5 6 7 8 9 101112 1314151617181920 A VSS VDD RPOS1 TSOFO1 TLCLK1 VSS B MODE ROHSOF 1 RNEG1 TCLKI1 TSOFI1 RLCLK1 RST* VDD C GPIO[5] GPIO[6] A[10] TPOS1 TOHSOF 1 TOHCLK1 D VDD_RX1 A[5] A[9] TNEG1 ROHCLK 1 TCLKO1 TOH1 RCLKO1 ROH1 E A[1] A[4] A[8] JTRST* TOHEN1 TSER1 RSOFO1 RSER1 F RXN1 RXP1 JTCLK JTMS GPIO[1] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD G VDD_JA1 A[3] A[7] JTDO GPIO[2] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD H A[0] A[2] A[6] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD J TXN1 TXP1 JTDI VDD_TX1 D[15] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS K CLKA RDY* RD* WR* VDD_CLA D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS L CLKB CLKC CS* INT* WIDTH VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS M TXN2 TXP2 TEST* VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N VDD_TX2 ALE D[6] D[11] VDD_JA2 VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD P D[0] D[2] D[7] D[12] GPIO[4] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD R RXN2 RXP2 HIZ* D[13] GPIO[3] VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD T VDD_RX2 D[3] D[8] D[14] TOHEN2 TSER2 RSOFO2 RSER2 ROH4 U D[1] D[4] D[9] TNEG2 ROHCLK 2 TCLKO2 TOH2 RCLKO2 ROH2 V GPIO[7] GPIO[8] D[10] TPOS2 TOHSOF 2 TOHCLK2 W VDD D[5] RNEG2 TCLKI2 TSOFI2 RLCLK2 Y VSS ROHSOF 2 RPOS2 TSOFO2 TLCLK2 VDD VSS Note: Green indicates VSS; red indicates VDD; blank cells indicate No Connect balls. |
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