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Table 13-1. JTAG Instruction Codes

INSTRUCTIONS

SELECTED REGISTER

INSTRUCTION CODES

EXTEST

Boundary Scan

000

IDCODE

Device Identification

001

SAMPLE/PRELOAD

Boundary Scan

010

CLAMP

Bypass

011

HIGHZ

Bypass

100

—

Bypass

101

—

Bypass

110

BYPASS

Bypass

111

SAMPLE/PRELOAD. This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports

two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with

the normal operation of the device and the boundary scan register can be pre-loaded for the EXTEST instruction.

The positive edge of JTCLK in the Capture-DR state samples all digital input pins into the boundary scan register.

The boundary scan register is connected between JTDI and JTDO. The data on JTDI pin is clocked into the

boundary scan register and the data captured in the Capture-DR state is shifted out the TDO pin in the Shift-DR

state.

EXTEST. This is a mandatory instruction for the IEEE 1149.1 specification. This instruction allows testing of all

interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following

actions occur. Once enabled by the Update-IR state, the parallel outputs of all digital output pins are driven

according to the values in the boundary scan registers on the positive edge of JTCLK. The boundary scan register

is connected between JTDI and JTDO. The positive edge of JTCLK in the Capture-DR state samples all digital

input pins into the boundary scan register. The negative edge of JTCLK in the Update-DR state causes all of the

digital output pins to be driven according to the values in the boundary scan registers that have been shifted in

during the Shift-DR state. The outputs are returned to their normal mode or HIZ mode at the positive edge of

JTCLK during the Update-IR state when an instruction other than EXTEST or CLAMP is activated.

BYPASS. This is a mandatory instruction for the IEEE 1149.1 specification. When the BYPASS instruction is

latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This

allows data to pass from JTDI to JTDO not affecting the device’s normal operation. This mode can be used to

bypass one or more chips in a system with multiple chips that have their JTAG scan chain connected in series. The

chips not in bypass can then be tested with the normal JTAG modes.

IDCODE. This is a mandatory instruction for the IEEE 1149.1 specification. When the IDCODE instruction is

latched into the parallel instruction register, the identification test register is selected. The device identification code

is loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-

DR can be used to shift the identification code out serially through JTDO. During Test-Logic-Reset, the

identification code is forced into the instruction register’s parallel output.

HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI

and JTDO. The outputs are put into the HIZ mode when the HIZ instruction is loaded in the Update-IR state and on

the positive edge of JTCLK. The outputs are returned to their normal mode or driven from the boundary scan

CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass

instruction was not EXTEST, the outputs will be driven according to the values in the boundary scan register at the

positive edge of JTCLK in the Update-IR state. The typical use of this instruction is in a system that has the JTAG

scan chain of multiple chips connected in series, and all of the chips have their outputs initialized using the

EXTEST mode. Then some of the chips are left initialized using the CLAMP mode and others have their IO

controlled using the EXTEST mode. This reduces the size of the scan chain during the partial testing of the system.

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