DS3172 datasheet(207/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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13 JTAG INFORMATION

13.1 JTAG Description

This device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public

instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following items, which meet the

requirements set by the IEEE 1149.1 Standard Test Access Port (TAP) and Boundary Scan Architecture:

Test Access Port (TAP)

TAP Controller

Instruction Register

Bypass Register

Boundary Scan Register

Device Identification Register

The Test Access Port has the necessary interface pins, namely JTCLK, JTDI, JTDO, and JTMS, and the optional

JTRST input. Details on these pins can be found in Section 8. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and

IEEE 1149.1b-1994 for details about the Boundary Scan Architecture and the Test Access Port.

Figure 13-1. JTAG Block Diagram

Boundary Scan

Identification

Bypass

Instruction

Test Access Port

Controller

Mux

Select

Tri-State

JTDI

10K

JTMS

10K

JTCLK

JTRST

10K

JTDO

13.2 JTAG TAP Controller State Machine Description

This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. See

Figure 13-2 for details on each of the states described below. The TAP controller is a finite state machine that

responds to the logic level at JTMS on the rising edge of JTCLK.

DS3172 Datasheet(PDF) 207 Page - Dallas Semiconductor