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DS3172 Datasheet(PDF) 205 Page - Dallas Semiconductor

Part # DS3172
Description  Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
PDF  232 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3172 Datasheet(HTML) 205 Page - Dallas Semiconductor

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12.9.8 Receive Clear Channel
The receive Clear Channel mode utilizes four registers.
12.9.8.1 Register Map
Table 12-30. Receive Clear Channel Register Map
Address
Register
Register Description
(1,3,5,7)20h
CC.RCR
Clear Channel Receive Control Register
(1,3,5,7)22h
--
Reserved
(1,3,5,7)24h
CC.RSR1
Clear Channel Receive Status Register #1
(1,3,5,7)26h
--
Reserved
(1,3,5,7)28h
CC.RSRL1 Clear Channel Receive Status Register Latched #1
(1,3,5,7)2Ah
--
Reserved
(1,3,5,7)2Ch CC.RSRIE1 Clear Channel Receive Status Register Interrupt Enable #1
(1,3,5,7)2Eh
--
Reserved
(1,3,5,7)30h
--
Reserved
(1,3,5,7)32h
--
Reserved
(1,3,5,7)34h
--
Reserved
(1,3,5,7)36h
--
Reserved
(1,3,5,7)38h
--
Reserved
(1,3,5,7)3Ah
--
Reserved
(1,3,5,7)3Ch
--
Unused
(1,3,5,7)3Eh
--
Unused
12.9.8.2 Register Bit Descriptions
Register Name:
CC.RCR
Register Description:
Clear Channel Receive Control Register
Register Address:
(1,3,5,7)20h
Bit #
15
14
13
12
11
10
9
8
Name
Reserved
Reserved
Reserved
MDAISI
AAISD
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
0
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS condition will cause
downstream AIS to be inserted. When 1, the presence of an LOS condition will not cause downstream AIS to be
inserted.



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