DS3172 datasheet(202/232 Pages) DALLAS

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Bit 2: Remote Error Indication Count Interrupt Enable (FBECIE) – This bit enables an interrupt if the FBECL bit

is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 1: Parity Error Count Interrupt Enable (PECIE) – This bit enables an interrupt if the PECL bit is set and the

bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 0: Framing Error Count Interrupt Enable (FECIE) – This bit enables an interrupt if the FECL bit is set and the

bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.

0 = interrupt disabled

1 = interrupt enabled

E3G832.RMABR

E3 G.832 Receive MA Byte Register

(1,3,5,7)30h

Bit #

Name

Default

Bit #

Name

RPT2

RPT1

RPT0

TI3

TI2

TI1

TI0

Default

Bits 6 to 4: Receive Payload Type (RPT[2:0]) – These three bits are the integrated version of the payload type

(MA[3:5]) from the MA byte.

Bits 3 to 0: Receive Timing Source Indication (TI[3:0]) – When timing source indicator extraction is enabled,

these four bits are the integrated version of the four timing source indicator bits extracted from the last three bits of

the MA byte (MA[6:8]). When timing source indicator bit extraction is disabled, TI[3] is zero, and TI[2:0] contain the

integrated version of the last three bits of the MA byte.

E3G832.RNGBR

E3 G.832 Receive NR and GC Byte Register

(1,3,5,7)32h

Bit #

Name

RGC7

RGC6

RGC5

RGC4

RGC3

RGC2

RGC1

RGC0

Default

Bit #

Name

RNR7

RNR6

RNR5

RNR4

RNR3

RNR2

RNR1

RNR0

Default

Bits 15 to 8: Receive GC Byte (RGC[7:0]) – These eight bits are the integrated version of the GC byte as

extracted from the E3 frame.

Bits 7 to 0: Receive NR Byte (RNR[7:0]) – These eight bits are the integrated version of the NR byte as extracted

from the E3 frame.

DS3172 Datasheet(PDF) 202 Page - Dallas Semiconductor

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