DS3172 datasheet(208/232 Pages) DALLAS

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Figure 13-2. JTAG TAP Controller State Machine

Test-Logic-Reset

Run-Test/Idle

Select

DR-Scan

Capture-DR

Shift-DR

Exit1- DR

Pause-DR

Exit2-DR

Update-DR

Select

IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Test-Logic-Reset. When

JTRST is changed from low to high, the TAP controller starts in the Test-Logic-Reset

state, and the Instruction Register is loaded with the IDCODE instruction. All system logic and I/O pads on the

device operate normally. This state can also be reached from any other state by holding JTMS high and clocking

JTCLK five times.

Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The Instruction Register

and Test Register remain idle.

Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the

controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-

IR-Scan state.

Capture-DR. Data may be parallel loaded into the Test Data register selected by the current instruction. If the

instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test Register

remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or

to the Exit1-DR state if JTMS is high.

Shift-DR. The Test Data Register selected by the current instruction is connected between JTDI and JTDO and

shifts data one stage towards its serial output on each rising edge of JTCLK. If a Test Register selected by the

current instruction is not placed in the serial path, it maintains its previous state.

Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state

that terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR

state.

DS3172 Datasheet(PDF) 208 Page - Dallas Semiconductor