SC3200 datasheet(211/447 Pages) AMD

211 / 447 page

AMD Geode™ SC3200 Processor Data Book

211

Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0

Revision 5.1

IDE Reset. Reset IDE bus.

0: Disable.

1: Enable (drive IDE_RST# low).

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

Note:

When X-Bus Warm Start is enabled (bit 0 = 1) or during POR#, IDE_RST# is put into TRI-STATE mode. To prop-

erly reset the IDE bus, after POR# the boot code must cause IDE_RST# to activate.

PCI Reset. Reset PCI bus.

0: Disable.

1: Enable.

When this bit is set to 1, the Core Logic module output signal PCIRST# is asserted and all devices on the PCI bus (including

PCIUSB) are reset. No other function within the Core Logic module is affected by this bit.

Write 0 to clear this bit. This bit is level-sensitive and must be cleared after the reset is enabled.

X-Bus Warm Start. Writing and reading this bit each have different meanings.

When reading this bit, it indicates whether or not a warm start occurred since power-up:

0: A warm start occurred.

1: No warm start has occurred.

When writing this bit, it can be used to trigger a system-wide reset:

0: No effect.

1: Execute system-wide reset (used only for clock configuration at power-up).

Index 45h

Reserved

Reset Value: 00h

Index 46h

PCI Functions Enable Register (R/W)

Reset Value: FEh

7:6

Reserved. Resets to 11.

F5 (PCI Function 5). When asserted (set to 1), enables the register space designated as F5.