PC8374L datasheet(235/239 Pages) NSC

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10.0 Device Characteristics (Continued)

Revision 1.1

235

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Main Power Supply Control

SMBus Voltage Translation and Isolation Timing

Symbol Figure

Description

Reference Conditions

Min

Max

Units

tPR

−

Rise Propagation Delay1,2

1. Not tested. Guaranteed by design.

2. Test conditions: CL = 50 pF and 1 KΩ external resistor to VSB5.

(CPU_PRESENT = 1) or (SLP_S3 = 0) or

(ETC event occurred) to RE of PS_ON

µs

tPF

−

Fall Propagation Delay1

From whichever occurs last:

(CPU_PRESENT = 0), (SLP_S3 = 1), (No

ETC event and RE on SLP_S3)

to FE of PS_ON

µs

−

Rise Time1,2

0.8V to 2.0V

−

Fall Time1

2.0V to 0.8V

Symbol

Figure

Description

Type of

Requirement1

1. An “Input” type is a value the PC8374L device expects from the system; an “Output” type is a value the

PC8374L device provides to the system.

Min

Max

Unit

tSMBR

−

Rise Time (all signals)

Input

10002,3

2. Test conditions: RL = 1 KΩ to VDD3 = 2.25V or 3.3V, or RL = 1.5 KΩ to VDD5 = 5V and CL = 400 pF to GND.

3. Not tested. Guaranteed by design.

tSMBF

−

Fall Time (all signals)

Input

2503

Output

3002,4

4. Not tested. Guaranteed by characterization.

tSMBD

−

Propagation Delay (each signal pair, in both

directions)

Output

5002,4

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PC8374L Datasheet(PDF) 235 Page - National Semiconductor (TI)

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