PC8374L datasheet(236/239 Pages) NSC

236 / 239 page

10.0 Device Characteristics (Continued)

www.national.com

236

Revision1.1

10.4.10

SWC Timing

Wake-Up Inputs at VSB3 Power Switching

Figure 56. Inputs at VSB3 Power Switching

Wake-Up Inputs at VDD3 Power Switching

Figure 57. Wake-Up Inputs at VDD3 Power Switching

Symbol

Figure

Description

Reference Conditions

Min

Max

tEWIV

External Wake-Up Inputs Valid1

1. Not tested. Guaranteed by characterization.

At VSB3 power on, after the

32 KHz Domain is toggling

24576 * tCP

2. tCP is the cycle time of the 32 KHz clock domain (see “Low-Frequency Clock Timing” on page 223).

32768 * tCP

Symbol

Figure

Description

Reference Conditions

Min

Max

tEWIV

External Wake-Up Inputs Valid1

1. Not tested. Guaranteed by characterization.

After VDD3 power on

2. The 32 KHz clock domain is assumed to be toggling at VDD3 power stable.

24576 * tCP

3. tCP is the cycle time of the 32 KHz clock domain (see “Low-Frequency Clock Timing” on page 223).

32768 * tCP

VSB3 (Power)

GPIOE14-10,

tEWIV

GPIOE07-00,

KBCLK, MCLK

VSB3OFF

VSB3ON

KBDAT, MDAT

(Internal)

VSB Power-Up Reset

t32KW + t32KVAL

tIRST

32 KHz Domain

(Internal)

GPIOE17-16,

VDD3 (Power)

GPIOE17-16,

tEWIV

VDD3OFF

VDD3ON

(VDDLOAD = 1)

GPIOE07-00

GPIOE14

-10,

Winbond Electronics Corp. Advanced PC Product Center

PC8374L Datasheet(PDF) 236 Page - National Semiconductor (TI)

PC8374L Datasheet(HTML) 236 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL