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PC8374L Datasheet(PDF) 237 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 237 Page - National Semiconductor (TI) |
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237 / 239 page  10.0 Device Characteristics (Continued) Revision 1.1 237 www.national.com 10.4.11 SMBus Timing Figure 58. SMBus Signals (HMSCL and HMSDA) Rising Time and Falling Time Symbol Figure Description Type of Requirement1 1. An “Input” type is a value the PC8374L expects from the system; an “Output” type is a value the PC8374L provides to the system. Min Max Unit tSMBR 58 Rise time (HMSCL and HMSDA) Input2 2. Test conditions: RL = 1 KΩ to VSB = 3.3V, CL = 400 pF to GND. 10003 3. Not tested. Guaranteed by design. ns tSMBF 58 Fall time (HMSCL and HMSDA) Input 3003 ns Output2 2504 4. Not tested. Guaranteed by characterization. ns tSMBCKL 58 Clock low period (HMSCL) Input 4.7 µs tSMBCKH 58 Clock high period (HMSCL) Input 4 µs tSMBCY 59 Clock cycle (HMSCL) Input 10 µs tSMBDS 59 Data setup time (before clock rising edge) Input 250 ns Output2 250 ns tSMBDH 59 Data hold time (after clock falling edge) Input 0 ns Output2 300 ns tSMBPS 60 Stop condition setup time (clock before data) Input 4 µs tSMBSH 60 Start condition hold time (clock after data) Input 4 µs tSMBBUF 60 Bus free time between Stop and Start conditions (HMSDA) Input 4.7 µs tSMBRS 61 Restart condition setup time (clock before data) Input 4.7 µs tSMBRH 61 Restart condition hold time (clock after data) Input 4 µs tSMBLEX - Cumulative clock low extend time from Start to Stop (HMSCL) Output 253 ms tSMBTO - Clock low time-out (HMSCL) Input 253,5 5. The PC8374L detects a time-out condition if HMSCL is held low for more than tSMBTO. ms Output 353,6 6. On detection of a time-out condition, the PC8374L resets the SMBus Interface no later than tSMBTO. ms tSMBR 2.5V 0.4V tSMBF 3.0V 0.4V 2.5V 0.4V 0.4V tSMBCKH tSMBCKL Winbond Electronics Corp. Advanced PC Product Center |
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