AM625 datasheet(91/235 Pages) TI

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over operating junction temperature range (unless otherwise noted)

SUPPLY NAME

DESCRIPTION

MIN(1)

NOM

MAX(1)

UNIT

Operating junction temperature range

Automotive

-40

125

°C

Extended

-40

105

°C

Commercial

°C

(1)

The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during

normal device operation.

(2)

VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 shall be sourced from the same power source.

Care should be taken to ensure that voltage differential between VDD_CORE and VDDA_CORE_USB is within +/- 1%.

(3)

The VDDA_DDR_PLL0 power rail is only available on the AMC package. This power rail is internally connected to VDD_CORE in the

ALW package.

(4)

VDD_CANUART and VDDSHV_CANUART shall be connected to always on power sources when using Partial IO low power mode.

VDD_CANUART shall be connected to the same power source as VDD_CORE and VDDSHV_CANUART shall be connected to any

valid IO power source when not using Partial IO low power mode.

(5)

VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.

(6)

The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.2.4, System Power

Supply Monitor Design Guidelines.

(7)

An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.2.3, USB

Design Guidelines.

7.5 Operating Performance Points

This section describes maximum operating conditions of the device in Table 7-1 and describes each Operating

Performance Point (OPP) for processor clocks and device core clocks in Table 7-2.

Table 7-1. Device Speed Grades

Speed

Grade

VDD_CORE

(V)(1)

MAXIMUM OPERATING FREQUNCY (MHz)

MAXIMUM

TRANSITION

RATE (MT/s)(2)

A53SS

(Cortex-

A53x)

GPU

PRU

Main

Infra

(CBA)

MCUSS

(Cortex-

M4F)

Device

Manager

(Cortex-

R5F)

SMS

Subsystem

(Dual

Cortex-

M4F)

OCSRAM

DDR4

LPDDR4

0.75/0.85

800

500

333

250

400

1600

0.75/0.85

1000

500

333

250

400

1600

0.75/0.85

1250

500

333

250

400

1600

0.85

1400

(1)

Nominal operating voltage, see Recommended Operating Conditions.

(2)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.

Table 7-2. Device Operating Performance Points

OPP

A53SS(1)

FIXED OPERATING FREQUENCY OPTIONS (MHz)(2)

MT/s(3)

GPU

PRU

MAIN

INFRA (CBA)

MCUSS

DEVICE

MANAGER

SMS /

SMS CBA

OCSRAM

DDR4

LPDDR4

High

From

ARM0

PLL

Bypass

Speed

Grade

Maximum

500

333,

250,

200

250

400

200

400

1600

(Max)

From

DDR

PLL

Bypass(4)

1600

Low

N/A

125

133

250

(DRAM DLL

Bypass)

(1)

Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.

(2)

Fixed operating frequency, set by software at boot.

(3)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.

(4)

The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL

Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.

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SPRSP58 – JUNE 2022

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