CS48L32 datasheet(56/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

4.3 Digital Core

The DRC2 control registers are described in Table 4-16.

R43784 (0xAB08)

DRC1_CONTROL3

15:12 DRC1_NG_

MINGAIN[3:0]

0000 DRC1 Minimum gain to attenuate audio signals when the Noise Gate is active.

0000 = –36 dB

0001 = –30 dB

0010 = –24 dB

0011 = –18 dB

0100 = –12 dB

0101 = –6 dB

0110 = 0 dB

0111 = 6 dB

1000 = 12 dB

1001 = 18 dB

1010 = 24 dB

1011 = 30 dB

1100 = 36 dB

1101 to 1111 = Reserved

11:10 DRC1_NG_

EXP[1:0]

DRC1 Noise-Gate slope

00 = 1 (no expansion)

01 = 2

10 = 4

11 = 8

9:8 DRC1_QR_

THR[1:0]

DRC1 Quick-release threshold (crest factor in dB)

00 = 12 dB

01 = 18 dB

10 = 24 dB

11 = 30 dB

7:6 DRC1_QR_

DCY[1:0]

DRC1 Quick-release decay rate (seconds/6 dB)

00 = 0.725 ms

01 = 1.45 ms

10 = 5.8 ms

11 = Reserved

5:3 DRC1_HI_

COMP[2:0]

011

DRC1 Compressor slope (upper region)

000 = 1 (no compression)

001 = 1/2

010 = 1/4

011 = 1/8

100 = 1/16

101 = 0

11X = Reserved

2:0 DRC1_LO_

COMP[2:0]

000

DRC1 Compressor slope (lower region)

000 = 1 (no compression)

001 = 1/2

010 = 1/4

011 = 1/8

100 = 0

101 = Reserved

11X = Reserved

R43788 (0xAB0C)

DRC1_CONTROL4

28:24 DRC1_KNEE2_

IP[4:0]

0x00 DRC1 Input signal level at the noise-gate threshold (Knee 2).

0x00 = –36 dB

0x01 = –37.5 dB

0x02 = –39 dB

… (-1.5 dB steps)

0x1E = –81 dB

0x1F = –82.5 dB

Applicable if DRC1_NG_EN = 1

20:16 DRC1_KNEE2_

OP[4:0]

0x00 DRC1 Output signal at the noise-gate threshold (Knee 2).

0x00 = –30 dB

0x01 = –31.5 dB

0x02 = –33 dB

… (–1.5 dB steps)

0x1E = –75 dB

0x1F = –76.5 dB

Applicable only if DRC1_KNEE2_OP_EN = 1

13:8 DRC1_KNEE1_

IP[5:0]

0x00 DRC1 Input signal level at the compressor knee (Knee 1).

0x00 = 0 dB

0x01 = –0.75 dB

0x02 = –1.5 dB

… (–0.75 dB steps)

0x3C = –45 dB

0x3D–0x3F = Reserved

4:0 DRC1_KNEE1_

OP[4:0]

0x00 DRC1 Output signal at the compressor knee (Knee 1).

0x00 = 0 dB

0x01 = –0.75 dB

0x02 = –1.5 dB

… (–0.75 dB steps)

0x1E = –22.5 dB

0x1F = Reserved

Table 4-16. DRC2 Control Registers

Bit

Label

Default

Description

R43012 (0xA804)

FX_STATUS

15:4 FX_STS[11:0]

0x00

LHPF, DRC, EQ Enable Status. Indicates the status of each respective

signal-processing function. Each bit is coded as follows:

0 = Disabled

1 = Enabled

[11] = EQ4

[10] = EQ3

[9] = EQ2

[8] = EQ1

[7] = DRC2 (Right)

[6] = DRC2 (Left)

[5] = DRC1 (Right)

[4] = DRC1 (Left)

[3] = LHPF4

[2] = LHPF3

[1] = LHPF2

[0] = LHPF1

Table 4-15. DRC1 Control Registers (Cont.)

Bit

Label

Default

Description

CS48L32 Datasheet(PDF) 56 Page - Cirrus Logic

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