CS48L32 datasheet(6/192 Pages) CIRRUS

6 / 192 page

Cirrus Logic

DS1219F4

CS48L32

1.3 Pin Descriptions

SPI1_MISO

VDD_IO

SPI1 control interface Master In Slave Out data.

SPI1_MISO is high impedance if SPI1_SS is not

asserted.

Z/C

Output

SPI1_MOSI

VDD_IO

SPI1 control interface Master Out Slave In data

H/OD

Input

SPI1_SCK

VDD_IO

SPI1 control interface clock input

Input

SPI1_SS

VDD_IO

SPI1 control interface slave select

Input

SPI2_SCK/

GPIO12

VDD_IO

I/O

SPI master interface clock output/GPIO12

PU/PD/K/H/

C/OD

GPIO12 input

with bus-keeper

SPI2_SIO0/

GPIO13

VDD_IO

I/O

SPI master interface Data 0 input/output/

GPIO13

PU/PD/K/H/

C/OD

GPIO13 input

with bus-keeper

SPI2_SIO1/

GPIO14

VDD_IO

I/O

SPI master interface Data 1 input/output/

GPIO14

PU/PD/K/H/

C/OD

GPIO14 input

with bus-keeper

SPI2_SIO2/

GPIO15

VDD_IO

I/O

SPI master interface Data 2 input/output/

GPIO15

PU/PD/K/H/

C/OD

GPIO15 input

with bus-keeper

SPI2_SIO3/

GPIO16

VDD_IO

I/O

SPI master interface Data 3 input/output/

GPIO16

PU/PD/K/H/

C/OD

GPIO16 input

with bus-keeper

SPI2_SS/

GPIO11

VDD_IO

I/O

SPI master interface slave select/GPIO11

PU/PD/K/H/

C/OD

GPIO11 input

with bus-keeper

Supply

GND_A

GND [2]

—

Analog ground (return path for VDD_A)

—

GND_CP

A8, B7

GND [2]

—

Charge pump ground (return path for VDD_CP)

—

GND_D

E1, G3,

GND [2]

—

Digital ground (return path for VDD_D and VDD_

IO)

——

GND_SUB

A1, A2,

GND [2]

—

Substrate ground (also return path for VDD_

FLL)

——

VDD_A

—

Analog supply

—

VDD_D

D1, H6

20, 43

—

Digital core supply

—

VDD_FLL

—

Analog FLL supply

—

VDD_IO

—

Digital buffer (I/O) supply

—

VDD_CP

—

Analog supply for Charge Pump

—

No Connect

C1, C2,

C3, F8,

H1, H8

11, 12,

13, 14,

35, 36,

37, 38,

39, 44,

45, 46,

47, 48, 49

——

—

1.The analog input functions on these pins are referenced to the VOUT_MIC power domain. The digital input/output functions are referenced to the

VOUT_MIC or MICBIAS1 power domain, as selected by the applicable INn_PDM_SUP field.

2.On the QFN package variant, all of the CS48L32 ground domains are connected to the exposed die pad.

Table 1-1. Pin Descriptions (Cont.)

PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain.

Pin Name

Pin #

(WLCSP)

Pin #

(QFN)

Power

Supply

I/O

Pin Description

Digital Pad

Attributes

State at Reset

CS48L32 Datasheet(PDF) 6 Page - Cirrus Logic

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