CS48L32 datasheet(8/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-1 defines parameters as they are characterized in this section.

Table 3-1. Parameter Definitions

Parameter

Definition

Channel separation

Left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to

maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active

channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured

at the output of the associated idle channel.

Common-mode rejection

ratio (CMRR)

The ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that

results from it.

Power-supply rejection

ratio (PSRR)

The ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured

under quiescent signal path conditions.

Signal-to-noise ratio

(SNR)

A measure of the difference in level between the maximum full scale output signal and the output with no input signal

applied.

Total harmonic distortion

(THD)

The ratio of the RMS sum of the harmonic distortion products in the specified bandwidth 1 relative to the RMS

amplitude of the fundamental (i.e., test frequency) output.

1.All performance measurements are specified with a 20 kHz, low-pass brick-wall filter and, where noted, an A-weighted filter. The low-pass filter

removes out-of-band noise.

Total harmonic distortion

plus noise (THD+N)

The ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth 1 relative to the

RMS amplitude of the fundamental (i.e., test frequency) output.

Table 3-2. Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits.

Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified.

Parameter

Symbol

Minimum

Maximum

Supply voltages

VDD_D [1], VDD_FLL [1]

VDD_A, VDD_CP

VDD_IO

1.The VDD_D and VDD_FLL pins should be tied to a common supply rail. The associated power domain is referred to as VDD_D.

–0.3 V

1.52 V

2.27 V

4.32 V

Voltage range digital inputs

VDD_IO domain

INn_PDMDATA

—

VGND_SUB – 0.3 V

VVDD_IO + 0.3 V

VVOUT_MIC + 0.3 V

Voltage range analog inputs

IN1xx_n

VGND_SUB – 0.3 V

VVOUT_MIC + 0.3 V

Ground 2

2.On the QFN package variant, all of the CS48L32 ground domains are connected to the exposed die pad.

GND_A, GND_D, GND_CP

VGND_SUB – 0.3 V

VGND_SUB + 0.3V

Operating temperature range

–40ºC

+85ºC

Operating junction temperature

–40ºC

+125ºC

Storage temperature after soldering

—

–65ºC

+150ºC

ESD-sensitive device. The CS48L32 is manufactured on a CMOS process. It is therefore generically susceptible to damage from

excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. This device is qualified

to current JEDEC ESD standards.

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