CS48L32 datasheet(80/192 Pages) CIRRUS

80 / 192 page

Cirrus Logic

DS1219F4

CS48L32

4.5 DSP Peripheral Control

A maximum of one event per cycle of the clock source can be logged. If more than one event occurs within the cycle time,

the highest priority (lowest channel number) event is logged at the rising edge of the clock. In this case, any lower priority

events are queued, and are logged as soon as no higher priority events are pending. It is possible for recurring events on

a high-priority channel to be logged, while low-priority ones remain queued. Note that recurring instances of queued events

are not logged.

The event logger can use a slow clock (e.g., 32 kHz), but higher clock frequencies may also be commonly used, depending

on the application and use case. The clock frequency determines the maximum possible event logging rate.

4.5.1.2

Event Logger Control

The event logger is enabled by setting EVENTLOG1_EN. The event logger can be reset by writing 1 to EVENTLOG1_

RST—executing this function clears all the event logger status flags and clears the contents of the FIFO buffer.

The associated timer (and time-stamp source) is selected using EVENTLOG1_TIMER_SEL. Note that the event logger

must be disabled (EVENTLOG1_EN = 0) when changing the timer source.

4.5.1.3

Input Channel Configuration

The event logger allows up to 16 input channels to be configured for detection and logging. The EVENTLOG1_CHx_SRC

field selects the applicable input source for each channel (where x identifies the channel number, 1 to 16). The polarity

selection and debounce options are configured using the EVENTLOG1_CHx_POL and EVENTLOG1_CHx_DB bits

respectively. The debounce time is configurable using EVENTLOG1_DBTIME.

To avoid filling the FIFO buffer with repeated instances of any event, a selectable filter is provided for each input channel.

If the EVENTLOG1_CHx_FILT bit is set, new events on the respective channel are ignored by the event logger if the

unread entries in the FIFO buffer indicate a previous event of the same type (i.e., same input source and same polarity).

The read/write pointers of the FIFO buffer (see Section 4.5.1.4) are used to determine which FIFO entries are unread (i.e.,

have not yet been read by the host processor).

The input channels can be enabled or disabled freely, using EVENTLOG1_CHx_EN, without having to disable the event

logger entirely. An input channel must be disabled whenever the associated x_SRC, x_FILT, x_POL, or x_DB fields are

written. It is possible to reconfigure input channels while the event logger is enabled, provided the channels being

reconfigured are disabled when doing so.

The available input sources include FLL-lock status, input-path signal detection, GPIO inputs and signals generated by

the integrated Halo Core DSP. A list of the valid input sources for the event logger is provided in Table 4-30. Note that, to

log both rising and falling events from any source, two separate input channels must be configured—one for each polarity.

If an input channel is configured for rising edge detection (EVENTLOG1_CHx_POL = 0), and the corresponding input

signal is asserted (Logic 1) at the time when the event logger is enabled, an event is logged in respect of this initial state.

Similarly, if an input channel is configured for falling edge detection, and is deasserted (Logic 0) when the event logger is

enabled, a corresponding event is logged. If rising and falling edges are both configured for detection, an event is always

logged in respect of the initial condition.

4.5.1.4

FIFO Buffer

Each event (signal transition) that meets the criteria of an enabled channel is written to the 16-stage FIFO buffer. The

buffer is filled cyclically, but does not overwrite unread data when full. A status bit is provided to indicate if the buffer fills

up completely.

Note that the FIFO behavior is not enforced or fully implemented in the device hardware, but assumes that a compatible

software implementation is in place. New events are written to the buffer in a cyclic manner, but the data can be read out

in any order, if desired. The designed FIFO behavior requires the software to update the read pointer (RPTR) in the

intended manner for smooth operation.

The entire contents of the 16-stage FIFO buffer can be accessed directly in the register map. Each FIFO index (y = 0 to

15) comprises the EVENTLOG1_FIFOy_ID (identifying the source signal of the associated log event), the EVENTLOG1_

FIFOy_POL (the polarity of the respective event transition), and the EVENTLOG1_FIFOy_TIME field (containing the 32-bit

time stamp from the timer).

CS48L32 Datasheet(PDF) 80 Page - Cirrus Logic

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