CS48L32 datasheet(20/192 Pages) CIRRUS

20 / 192 page

Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-20. JTAG Interface Timing

Test conditions (unless specified otherwise): CLOAD = 25 pF (output pins); TCK slew (20%–80%) = 5ns; with the exception of the conditions noted,

the following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter 1

1.JTAG Interface timing

Symbol

Minimum

Typical

Maximum

Units

TCK cycle time

TCCY

—

TCK pulse width high

TCCH

—

TCK pulse width low

TCCL

—

TMS setup time to TCK rising edge

TMSU

1—

—

TMS hold time from TCK rising edge

TMH

2—

—

TDI setup time to TCK rising edge

TDSU

1—

—

TDI hold time from TCK rising edge

TDH

2—

—

TDO propagation delay from TCK falling edge

TDD

0—

TRST setup time to TCK rising edge

TRSU

3—

—

TRST hold time from TCK rising edge

TRH

3—

—

TRST pulse-width low

—

Table 3-21. Typical Signal Latency

Test conditions (unless specified otherwise):

VDD_IO = VDD_CP = VDD_A = 1.8 V, VDD_D = VDD_FLL = 1.2 V; VOUT_MIC = Off (CP2 and LDO2 disabled); TA = +25ºC; Fs = 48 kHz; 24-bit audio

data, I2S Slave Mode.

Operating Configuration

Latency (

s)

ADC to ASP path—analog input (INn) to digital output (ASPn) 1

1.Digital core high-pass filter is included in the signal path.

192 kHz input, 192 kHz output, Synchronous

96 kHz input, 96 kHz output, Synchronous

48 kHz input, 48 kHz output, Synchronous

44.1 kHz input, 44.1 kHz output, Synchronous

16 kHz input, 16 kHz output, Synchronous

8 kHz input, 8 kHz output, Synchronous

8 kHz input, 48 kHz output, Isochronous 2

16 kHz input, 48 kHz output, Isochronous 2

2.Signal is routed via the ISRC function in the isochronous cases only.

100

195

215

560

1170

1700

865

TCK

(input)

tCCH

tCCL

tCCY

TDI

(input)

tDSU

tDH

TMS

(input)

tMSU

tMH

TDO

(output)

tDD

TRST

(input)

tRSU

tRH

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