CS48L32 datasheet(26/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

4.2 Input Signal Path

4.2.2

Analog Line Input

Line inputs can be connected to the CS48L32 in a similar manner to the mic inputs. Single-ended and differential

configurations are supported on each analog input path, using the IN1x_SRC bits as described in Section 4.2.6.

The analog line input configurations are shown in Fig. 4-8 and Fig. 4-9. Note that the microphone bias (MICBIAS) is not

used for line input connections.

4.2.3

PDM (DMIC) Input

The CS48L32 supports as many as four PDM input channels, ideal for use with digital microphone (DMIC) input and other

digital interfaces. The IN1 input path supports analog and digital input; digital (PDM) operation is selected using IN1_

MODE as described in Section 4.2.6.

In PDM mode, two channels of audio data are multiplexed on the associated INn_PDMDATA pin. Each stereo interface is

clocked using the respective INn_PDMCLK pin.

If PDM input is enabled, the CS48L32 outputs the CLK signal on the applicable INn_PDMCLK pins. The CLK frequency

is controlled by the respective INn_OSR field, as described in Table 4-1 and Table 4-3. Note that the input-path PDM

interfaces operate in Master Mode only—the clock (CLK) signal is generated by the CS48L32.

Note that, if ultrasonic signal detection or demodulation is enabled (see Section 4.2.9), the CLK frequency for the

respective input path must be 1.536 MHz or 3.072 MHz.

Note that, if the 384 kHz or 768 kHz CLK frequency is selected, the maximum valid sample rate for the respective paths

is restricted as described in Table 4-1. If the input sample rates are set globally using IN_RATE (i.e., IN_RATE_

MODE = 0), all input paths are affected similarly.

The system clock, SYSCLK, must be present and enabled if using the PDM inputs; see Section 4.8 for details of SYSCLK

and the associated registers.

The PDM clock frequencies in Table 4-1 assume that the SYSCLK frequency is a multiple of 6.144 MHz (SYSCLK_

FRAC = 0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC = 1), the PDM clock frequencies are

scaled accordingly.

Figure 4-8. Single-Ended Line Input

Figure 4-9. Differential Line Input

Table 4-1. PDM Clock Frequency

Condition

PDM Clock Frequency

Valid Sample Rates

Signal Passband

INn_OSR = 000

384 kHz

Up to 48 kHz

Up to 4 kHz

INn_OSR = 001

768 kHz

Up to 96 kHz

Up to 8 kHz

INn_OSR = 010

1.536 MHz

Up to 192 kHz

Up to 20 kHz

INn_OSR = 011

2.048 MHz

Up to 192 kHz

Up to 20 kHz

INn_OSR = 100

2.4576 MHz

Up to 192 kHz

Up to 20 kHz

INn_OSR = 101

3.072 MHz

Up to 192 kHz

Up to 20 kHz

INn_OSR = 110

6.144 MHz

Up to 192 kHz

Up to 96 kHz

GND

Line

To ADC

VREF

PGA

–

IN1LN,

IN1RN

IN1LP,

IN1RP

To ADC

VREF

Line

PGA

–

IN1LN,

IN1RN

IN1LP,

IN1RP

CS48L32 Datasheet(PDF) 26 Page - Cirrus Logic

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