CS48L32 datasheet(78/192 Pages) CIRRUS

78 / 192 page

Cirrus Logic

DS1219F4

CS48L32

4.4 DSP Firmware Control

The system-clock configuration provides input to the interrupt control circuit and can be used to trigger an interrupt event

if the DSP1 clock frequency is less than the requested frequency—see Section 4.9.

4.4.3.3

DSP Core Control

To enable firmware execution on the DSP block, the DSP must be enabled by setting DSP1_CCM_CORE_EN. Note that

the DSP firmware should be loaded, and the clocks configured, before the DSP is enabled. The DSP1_CCM_CORE_EN

bit must remain set while the program is running—including during the wait state.

The DSP core is held in its reset state if DSP1_CCM_CORE_EN = 0. The DSP core is also reset by writing 1 to DSP1_

CCM_CORE_RESET. Following a reset, the DSP commences code execution starting at the base address of the DSP

program memory.

Note: The DSP core is disabled by clearing DSP1_CCM_CORE_EN. After disabling the DSP core, it is recommended

to reset the entire DSP subsystem using DSP1_CORE_SOFT_RESET as described in Section 4.4.3.4.

4.4.3.4

DSP Subsystem Control

The DSP subsystem (including the core, stream-arbiter controllers, NMI configuration, watchdog timer, and DSP

clock-frequency configuration) is reset by writing 1 to DSP1_CORE_SOFT_RESET.

The stream-arbiter controllers are resynchronized by writing 1 to DSP1_STREAM_ARB_RESYNC. This can be used to

synchronize two or more controllers. The DSP1_STREAM_ARB_RESYNC_MSK field selects which controllers are

affected by the resynchronize action.

4.4.3.5

DSP Control Registers

The DSP clocking, code-execution, and watchdog control registers are described in Table 4-28.

The audio signal paths connecting to/from the DSP processing block are configured as described in Section 4.3. Note that

the DSP firmware must be loaded and enabled before audio signal paths can be enabled.

Table 4-28. DSP Control Registers

Bit

Label

Default

Description

DSP1 base address = 0x200_0000

base address + 0xB8_0000

DSPn_CLOCK_FREQ

15:0 DSPn_CLK_FREQ_SEL[15:0]

DSP clock frequency select

Coded as LSB = 1/64 MHz.

The DSP clock must be less than or equal to the clock

source frequency. The DSP clock is generated by

division of the clock source, and may differ from the

selected frequency. The DSP clock frequency can be

read from DSPn_CLK_FREQ_STS.

base address + 0xB8_0008

DSPn_CLOCK_STATUS

15:0 DSPn_CLK_FREQ_STS[15:0]

DSP clock frequency (read only). Only valid if the DSP

core is enabled. Coded as LSB = 1/64 MHz.

base address + 0xB8_0010

DSPn_CORE_SOFT_RESET

0DSPn_CORE_SOFT_RESET

Write 1 to reset the DSP subsystem, including the

core, stream arbiters, NMI, watchdog timer, and DSP

clock-frequency selection.

base address + 0xB8_0050

DSPn_STREAM_ARB_

CONTROL

0DSPn_STREAM_ARB_RESYNC

Write 1 to reset the stream arbiter controllers. Only

affects the controllers that are unmasked in DSPn_

STREAM_ARB_RESYNC_MSK.

base address + 0xBC_1000

DSPn_CCM_CORE_CONTROL

9DSPn_CCM_CORE_RESET

Write 1 to reset the DSP core.

0DSPn_CCM_CORE_EN

DSP enable. Controls the DSP firmware execution.

0 = Disabled

1 = Enabled

base address + 0xBC_5A00

DSPn_STREAM_ARB_

RESYNC_MSK1

7:0 DSPn_STREAM_ARB_RESYNC_

MSK[7:0]

Selects which stream-arbiter masters are reset by

DSPn_STREAM_ARB_RESYNC. For each master,

setting the respective bit enables that master to be

reset.

CS48L32 Datasheet(PDF) 78 Page - Cirrus Logic

CS48L32 Datasheet(HTML) 78 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL