CS48L32 datasheet(11/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-9. Digital Input/Output

The following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Digital I/O (except

INn_PDMDATA and

INn_PDMCLK) 1

1.Note that digital input pins should not be left floating. Undriven digital inputs can be held at Logic 0 or Logic 1 levels using pull resistors or bus-keeper

circuits if required.

Input HIGH level

VVDD_IO = 1.71–1.98 V

VVDD_IO = 2.25–2.75 V

VVDD_IO = 2.97–3.6 V

0.75

VVDD_IO

0.8

VVDD_IO

0.7

VVDD_IO

—

Input LOW level

VVDD_IO = 1.71–1.98 V

VVDD_IO = 2.25–2.75 V

VVDD_IO = 2.97–3.6 V

—

0.3

VVDD_IO

0.25

VVDD_IO

0.2

VVDD_IO

Output HIGH level (IOH =1 mA)

VVDD_IO = 1.71–1.98 V

VVDD_IO = 2.25–2.75 V

VVDD_IO = 2.97–3.6 V

0.75

VVDD_IO

0.65

VVDD_IO

0.7

VVDD_IO

—

Output LOW level (IOL = –1mA)

VVDD_IO = 1.71–1.98 V

VVDD_IO = 2.25–2.75 V

VVDD_IO = 2.97–3.6 V

—

0.25

VVDD_IO

0.3

VVDD_IO

0.15

VVDD_IO

Input capacitance

—

Input leakage

–10

—

A

Pull-up/pull-down resistance (where applicable)

—



DMIC I/O

(INn_PDMDATA and

INn_PDMCLK) 1,2

2.INn_PDMDATA and INn_PDMCLK are referenced to a selectable supply, VSUP, according to the INn_PDM_SUP fields.

INn_PDMDATA input HIGH level

0.65

 VSUP

——

INn_PDMDATA input LOW level

—

0.35

 VSUP

INn_PDMCLK output HIGH level

IOH = 1 mA

0.8

 VSUP

——

INn_PDMCLK output LOW level

IOL = –1 mA

—

0.2

 VSUP

Input capacitance

—

Input leakage

–1

—

A

GPIOn

Clock output frequency

GPIO pin as OPCLK or FLL output

—

MHz

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