CS48L32 datasheet(72/192 Pages) CIRRUS

72 / 192 page

Cirrus Logic

DS1219F4

CS48L32

4.4 DSP Firmware Control

The CS48L32 digital core incorporates a Halo Core DSP, capable of running a wide range of audio-enhancement

functions. Different firmware configurations can be loaded onto the DSP, enabling the CS48L32 to be highly customized

for specific application requirements. DSP firmware can be configured using software packages provided by Cirrus Logic,

such as the SoundClear suite of audio-processing algorithms.

R42256 (0xA510)

ISRC2_

CONTROL1

31:27 ISRC2_FSH[4:0]

0x00

ISRC2 High Sample Rate (Sets the higher of the ISRC2 sample rates)

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x03 = SAMPLE_RATE_4

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All ISRC2_DECn_SRC fields must be cleared before changing ISRC2_FSH.

15:11 ISRC2_FSL[4:0]

0x00

ISRC2 Low Sample Rate (Sets the lower of the ISRC2 sample rates)

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x03 = SAMPLE_RATE_4

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All ISRC2_INTn_SRC fields must be cleared before changing ISRC2_FSL.

R42260 (0xA514)

ISRC2_

CONTROL2

ISRC2_INT2_EN

ISRC2 INT2 Enable

Interpolation Channel 2 path from ISRC2_FSL rate to ISRC2_FSH rate

0 = Disabled, 1 = Enabled

ISRC2_INT1_EN

ISRC2 INT1 Enable

Interpolation Channel 1 path from ISRC2_FSL rate to ISRC2_FSH rate

0 = Disabled, 1 = Enabled

ISRC2_DEC2_EN

ISRC2 DEC2 Enable

Decimation Channel 2 path from ISRC2_FSH rate to ISRC2_FSL rate

0 = Disabled, 1 = Enabled

ISRC2_DEC1_EN

ISRC2 DEC1 Enable

Decimation Channel 1 path from ISRC2_FSH rate to ISRC2_FSL rate

0 = Disabled, 1 = Enabled

R42528 (0xA620)

ISRC3_

CONTROL1

31:27 ISRC3_FSH[4:0]

0x00

ISRC3 High Sample Rate (Sets the higher of the ISRC3 sample rates)

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x03 = SAMPLE_RATE_4

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All ISRC3_DECn_SRC fields must be cleared before changing ISRC3_FSH.

15:11 ISRC3_FSL[4:0]

0x00

ISRC3 Low Sample Rate (Sets the lower of the ISRC3 sample rates)

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x03 = SAMPLE_RATE_4

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All ISRC3_INTn_SRC fields must be cleared before changing ISRC3_FSL.

R42532 (0xA624)

ISRC3_

CONTROL2

ISRC3_INT2_EN

ISRC3 INT2 Enable

Interpolation Channel 2 path from ISRC3_FSL rate to ISRC3_FSH rate

0 = Disabled, 1 = Enabled

ISRC3_INT1_EN

ISRC3 INT1 Enable

Interpolation Channel 1 path from ISRC3_FSL rate to ISRC3_FSH rate

0 = Disabled, 1 = Enabled

ISRC3_DEC2_EN

ISRC3 DEC2 Enable

Decimation Channel 2 path from ISRC3_FSH rate to ISRC3_FSL rate

0 = Disabled, 1 = Enabled

ISRC3_DEC1_EN

ISRC3 DEC1 Enable

Decimation Channel 1 path from ISRC3_FSH rate to ISRC3_FSL rate

0 = Disabled, 1 = Enabled

Table 4-22. Digital-Core ISRC Control (Cont.)

Bit

Label

Default

Description

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