CS48L32 datasheet(9/192 Pages) CIRRUS

9 / 192 page

Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-3. Recommended Operating Conditions

Parameter

Symbol

Minimum

Typical

Maximum Units

Digital supply range 1

Digital supply range

1.The VDD_D and VDD_FLL pins should be tied to a common supply rail. The associated power domain is referred to as VDD_D.

Core and FLL

I/O

VDD_D, VDD_FLL

VDD_IO

1.14

1.71

1.2

1.8

1.26

3.6

Charge pump supply range

VDD_CP

1.71

1.8

1.89

Analog supply range

VDD_A

1.71

1.8

1.89

Ground 2,3

2.The impedance between GND_D, GND_A, GND_CP, and GND_SUB must not exceed 0.1

.

3.On the QFN package variant, all of the CS48L32 ground domains are connected to the exposed die pad.

GND_D, GND_A, GND_CP, GND_SUB

—

Power supply rise time 4,5

4.If the VDD_D rise time exceeds 2 ms, RESET must be asserted during the rise and held asserted until after VDD_D is within the recommended

operating limits.

5.The specified minimum power supply rise times assume a minimum decoupling capacitance of 100 nF per pin. However, Cirrus Logic strongly

advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed. The specified

minimum power supply rise times also assume a maximum PCB inductance of 10 nH between decoupling capacitor and pin.

VDD_D

All other supplies

—

2000

—

s

Operating temperature range

–40

—

ºC

Note: There are no power sequencing requirements; the supplies may be enabled and disabled in any order.

Table 3-4. Analog Input Signal Level—IN1xx

Test conditions (unless specified otherwise): VDD_A = 1.8V; with the exception of the condition noted, the following electrical characteristics are valid

across the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Full-scale input signal level (0 dBFS output)

Single-ended PGA input, 0 dB PGA gain

—

0.5

–6

—

VRMS

dBV

Differential PGA input, 0 dB PGA gain

—

VRMS

dBV

Notes:

• The full-scale input signal level is also the maximum analog input level, before clipping occurs.

• The maximum input signal level is reduced by 6 dB if mid-power configuration is selected.

• The full-scale input signal level changes in proportion with VDD_A. For differential input, it is calculated as VDD_A / 1.8.

• A 1.0VRMS differential signal equates to 0.5VRMS/–6dBV per input.

• A sinusoidal input signal is assumed.

Table 3-5. Analog Input Pin Characteristics

Test conditions (unless specified otherwise): TA = +25ºC; with the exception of the condition noted, the following electrical characteristics are valid across

the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Input resistance

Single-ended PGA input, All PGA gain settings

Differential PGA input, All PGA gain settings

10.5

—



Input capacitance

——

Table 3-6. Analog Input Gain—Programmable Gain Amplifiers (PGAs)

The following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Minimum programmable gain

—

Maximum programmable gain

—

Programmable gain step size

Guaranteed monotonic

—

Table 3-7. Digital Input Signal Level—INn_PDMDATA

The following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Full-scale input level 1

The digital input signal level is measured in dBFS, where 0 dBFS is a signal level equal to the full-scale range (FSR) of the PDM input. The

FSR is defined as the amplitude of a 1 kHz sine wave whose positive and negative peaks are represented by the maximum and minimum

digital codes respectively—this is the largest 1 kHz sine wave that can fit in the digital output range without clipping.

0 dBFS digital core input, 0 dB gain

—

–6

—

dBFS

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