LTC7813 datasheet(21/28 Pages) AD

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LTC7878

Rev. 0

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APPLICATIONS INFORMATION

produce the most improvement. Although all dissipative

elements in circuit produce losses, four main sources

account for most of the losses in LTC7878 circuits.

1. DC I2R Losses. These arise from the resistances

of the MOSFETs, sensing resistor, inductor and PC

board traces and cause the efficiency to drop at high

output currents.

2. MOSFET Transition Loss. This loss arises from the brief

amount of time switch A or switch C spends in the satu-

rated region during switch node transitions. It depends

upon the input voltage, load current, driver strength

and MOSFET capacitance, among other factors.

3. DRVCC Current. This is the sum of the MOSFET driver

and control currents. This loss can be reduced by

supplying DRVCC current through the EXTVCC pin

from a high efficiency source, such as the output

(if 7V < VOUT = < 20V) or alternate low voltage supply

if available.

4. CIN and COUT Loss. The input capacitor has the difficult

job of filtering the large RMS input current to the regu-

lator in buck mode. The output capacitor has the more

difficult job of filtering the large RMS output current in

boost mode. Both CIN and COUT are required to have

low ESR to minimize the AC I2R loss and sufficient

capacitance to prevent the RMS current from causing

additional upstream losses in fuses or batteries.

5. Other Losses. Optional Schottky diodes paralleled

switch B and D are responsible for conduction losses

during dead time. Inductor core loss should also be

considered. Switch C causes reverse recovery current

loss in boost mode.

When making adjustments to improve efficiency, the input

current is the best indicator of changes in efficiency. If one

makes a change and the input current decreases, then the

efficiency has increased. If there is no change in input

current, then there is no change in efficiency.

Parallel Operations

For output loads that demand high current, multiple

LTC7878s can be paralleled and daisy chained to run

out of phase to provide more output current without

increasing input and output voltage ripple. The SYNC

pin allows the LTC7878 to synchronize to the CLKOUT

signal of another LTC7878. The CLKOUT signal can be

connected to the SYNC pin of the following LTC7878

stage to line up both the frequency and the phase of the

entire system. Tying the PHASMD pin to GND, floating or

INTVCC generates a phase difference (between SW1 and

CLKOUT) of 180°, 120° or 90° respectively for 2, 3 or 4

ICs parallel operations.

Similar to other peak current mode controllers, LTC7878

may be paralleled with natural cycle-by-cycle current

sharing and no extra current sharing loop and stability

issues. When designing multiple ICs parallel operations,

always start from the single LTC7878 design and check

the output current capability and load current transient

stability. Then the LTC7878s can be paralleled by making

these connections.

• Tie All of the VFB Pins Together

• Tie All of the ITH Pins Together (Assuming ITHB Short

To ITH for Initial Debug)

• Tie All of the SS Pins Together

• Tie All of the RUN Pins Together

• Tie the Inputs of All Converters Together

• Tie the Outputs of All Converters Together

• Route One IC’s CLKOUT to Another IC’s SYNC Pin

Refer to the Typical Applications section for an example

of a 2-phase parallel operation design.

The LTC7878 may also be paralleled from different input

voltages for a redundancy design. Just do not tie SS and

RUN pin of the LTC7878s together and each LTC7878 can

start up with different input voltages to supply current

to a single output. Any one input voltage failure won’t

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