PCA9420 datasheet(16/87 Pages) NXP

16 / 87 page

NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

• A falling edge on ON key over a 200 µs

Condition 4) The device stays at VIN OVP condition with no any valid supply attached

at VBAT. In result, all enabled power rails have been off. The following condition re-

initiates the power-up sequence.

• The VIN goes below its VIN OVP hysteresis (typ 100 mV)

The power-up sequence by ON key=Low over the debounce time is described as shown

in Figure 7.

For the power-up sequence, the chip can set the default sequence per the customer

requirement at factory setting (i.e. MTP option), from one of the 64 options. Once the chip

enters the power-down stage, the power-down sequence is implemented as the reverse

of the power-up sequence (i.e., first up, last down).

aaa-033080

POWER-UP SEQUENCE

ON Key

Default-On Rails

Position 1

=1ms

SYSRSTn

POWER-OFF STATE

CONTROL BY PROCESSOR

TPWUP_DLY_INTERVAL

(ON Long-Press Timer, 4s,8s,12s or 16s)

tON_LONG_PRESS

90%

TON_DEBOUNCE

=200µs

NOTE: BUCK1, BUCK2, LDO1 and LDO2 can be assigned to any of positions 1 through 4.

Positions 1 through 4 are LDO1, BUCK2, LDO2, and BUCK1.

(NOTE)

=2ms

The ON Key shall be pulled high

to avoid power recycle initiated

by a programmed ON long-Press

timer expired

PWR_DN_EN bit=1

SHIP_EN_x bit=1

Position 4

POWER-DOWN SEQUENCE

TPWDOWN_DLY_INTERVAL

Figure 7. Power-up/down sequence

On-the-fly output voltage change sequence

On-the-fly output voltage change is defined as the following: for any output rail, its

output voltage changes from one level (initial level) to another level (target level). Note

this assumes the output rail is always enabled before and after the on-the-fly change

transition. It does not include the case when any output rail is changed from disabled

state to enabled state, or vice versa.

If a user prefers to change any rail voltage on-the-fly, depending on the scenarios listed

below, the chip behavior is described as follows:

1. While the chip remains in its current operation mode, and the user programs the

output voltage setting I2C register value or enables/disables any or some of output

voltage rail(s), the chip simply executes the I2C command

2. While the user chooses to switch modes, i.e. change mode between any of the two

mode settings among Mode 0/1/2/3, and if this involves on-the-fly voltage change for

one or some output rails, such change should occur simultaneously when the chip

switches from initial mode to the target mode.

CAUTION: The user should not send an I2C command related to changing the setting of

the output rails during the power up/down or mode setting change process.

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

16 / 87

PCA9420 Datasheet(PDF) 16 Page - NXP Semiconductors

PCA9420 Datasheet(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL