PCA9420 datasheet(10/87 Pages) NXP

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

8.2 ASYS

The ASYS pin serves as the input power pin for PSYS1, PSYS2 and LDO2. Internally by

default it’s powered by either VIN or VBAT, whichever is greater. The internal ASYS input

selection circuit ensures a seamless transition when its input source changes from VIN to

VBAT, or vice versa.

Through I2C register setting selection (ASYS_INPUT_SEL [1:0]), the user also has the

option to choose the ASYS input source. However, upon power cycling and/or chip reset,

the ASYS input source goes back to the default setting (option 1 below).

SYS_INPUT_SEL [1:0]

1. 2b’00: From either VBAT or VIN, whichever is greater (default setting);

2. 2b’01: From VBAT only;

3. 2b’10: From VIN only;

4. 2b’11: Disconnect from VBAT or VIN (not a normal operation condition, for

INTERNAL test purposes only).

An I2C programmable pre-warning ASYS voltage threshold (ASYS_PRE_WARNING

[1:0]) can also be used to indicate when ASYS voltage drops below the ASYS pre-

warning threshold voltage, which triggers an interrupt event.

If any peripheral regulators are connected to ASYS node, the ASYS node follows a VIN

voltage up to a programmed OVP threshold (either 5.5 V or 6 V) with a various voltage

difference depending on a load current.

8.3 VBAT_BKUP (back-up battery input)

Internally, the input power source for LDO1 is provided by either VBAT_BKUP or ASYS,

whichever is greater. When a coin cell battery (or similar battery) is used in the system

as a backup battery, it can be connected to VBAT_BKUP; thus the LDO1 is powered

by either ASYS or the backup battery. When no such backup battery is used, the

VBAT_BKUP pin should always be connected to VBAT.

8.4 ON

The ON pin has the following functions implemented:

1. ON pin has internal 1 MΩ pull-up resistor to either 2.5 V or VBAT depending on VBAT

voltage. If VBAT is less than 3 V, ON is pulled up to 2.5 V and if VBAT is greater than

3 V, it is pulled to VBAT.

Falling edge (filtered after deglitching time, 200 µs typ), active-LOW signal enables

the chip and starts the power-up sequence from STANDBY state. If the chip stays in

ship mode before applying ON falling edge, upon the filtered falling edge of the ON

pin, the chip exits ship mode to start up into Mode Setting 0.

If the device is already in the middle of power-up or power-down sequence, the falling

edge applied on the ON pin is ignored by the chip.

1. Long press (duration time, 4 s, 8 s, 12 s or 16 s, is programmable via I2C,

ON_GLT_LONG [1:0]). If the logic low signal is applied continuously over a

programmed duration, the chip gets reset and recycles all power rails to their default

values

2. Also, in mode setting 0, 1, 2, or 3, an I2C bit “ON_CFG_x“ (x=0, 1, 2, or 3) is

reserved; by setting its value to either 0 or 1, the user can configure whether a mode

setting switches back to Mode Setting 0 or not, upon a valid falling edge detected

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

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