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PCA9420 Datasheet(PDF) 84 Page - NXP Semiconductors

Part # PCA9420
Description  Power management IC for low-power microcontroller applications
PDF  87 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9420 Datasheet(HTML) 84 Page - NXP Semiconductors

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NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Tables
Tab. 1.
Ordering information ..........................................2
Tab. 2.
Ordering options ................................................2
Tab. 3.
Pin description ...................................................5
Tab. 4.
Mode selection by external pins
(MODESEL0, MODESEL1) .............................12
Tab. 5.
Regulator summary .........................................14
Tab. 6.
Device level protection features ...................... 24
Tab. 7.
I2C target address .......................................... 24
Tab. 8.
Register map ...................................................25
Tab. 9.
DEV_INFO register bit description .................. 27
Tab. 10. TOP_INT register bit description ..................... 27
Tab. 11. Sub_INT0 register bit description ....................28
Tab. 12. Sub_INT0_Mask bit description ...................... 29
Tab. 13. Sub_INT1 register bit description ....................30
Tab. 14. Sub_INT1_Mask register bit description ..........30
Tab. 15. Sub_INT2 register bit description ....................31
Tab. 16. Sub_INT2_Mask register bit description ..........32
Tab. 17. TOP_CNTL0 register bit description ................33
Tab. 18. TOP_CNTL1 register bit description ................34
Tab. 19. TOP_CNTL2 register bit description ................34
Tab. 20. TOP_CNTL3 register bit description ................35
Tab. 21. TOP_CNTL4 register bit description ................36
Tab. 22. CHG_CNTL0 register bit description ...............36
Tab. 23. CHG_CNTL1 register bit description ...............37
Tab. 24. Linear battery charger constant current
(CC) setting .....................................................37
Tab. 25. CHG_CNTL2 register bit description ...............37
Tab. 26. Linear battery charger top-off charge
current setting ................................................. 38
Tab. 27. CHG_CNTL3 register bit description ...............38
Tab. 28. Low battery charge current setting ..................39
Tab. 29. CHG_CNTL4 register bit description ...............39
Tab. 30. Dead charge timer setting ...............................40
Tab. 31. Dead battery charge current setting ................40
Tab. 32. CHG_CNTL5 register bit description ...............41
Tab. 33. VBATREG, linear battery charger regulated
battery voltage setting .....................................41
Tab. 34. CHG_CNTL6 register bit description ...............42
Tab. 35. CHG_CNTL7 register bit description ...............42
Tab. 36. Set the thermistor beta value selection
(Thermistor beta values below are defined
for (25/85°C) range) ........................................ 42
Tab. 37. Thermal regulation threshold setting ............... 43
Tab. 38. CHG_STATUS_0 register bit description .........43
Tab. 39. CHG_STATUS_1 register bit description .........44
Tab. 40. CHG_STATUS_2 register bit description .........44
Tab. 41. CHG_STATUS_3 register bit description .........45
Tab. 42. REG_STATUS register bit description .............46
Tab. 43. ACT_DISCHARGE_CNTL register bit
description ....................................................... 46
Tab. 44. MODECFG_0_0 register bit description .......... 47
Tab. 45. SW1 output voltage for Mode Setting 0 ...........47
Tab. 46. MODECFG_0_1 register bit description .......... 48
Tab. 47. SW2 default output voltage for mode
setting 0 ...........................................................48
Tab. 48. MODECFG_0_2 register bit description .......... 49
Tab. 49. LDO1 default output voltage for mode
setting 0 ...........................................................49
Tab. 50. MODECFG_0_3 register bit description .......... 50
Tab. 51. LDO2 default output voltage for mode
setting 0 ...........................................................50
Tab. 52. MODECFG_1_0 register bit description .......... 50
Tab. 53. SW1 output voltage for Mode Setting 1 ...........51
Tab. 54. MODECFG_1_1 register bit description .......... 51
Tab. 55. SW2 default output voltage for mode
setting 1 ...........................................................52
Tab. 56. MODECFG_1_2 register bit description .......... 52
Tab. 57. LDO1 default output voltage for mode
setting 1 ...........................................................53
Tab. 58. MODECFG_1_3 register bit description .......... 53
Tab. 59. LDO2 default output voltage for mode
setting 1 ...........................................................53
Tab. 60. MODECFG_2_0 register bit description .......... 54
Tab. 61. SW1 output voltage for Mode Setting 2 ...........54
Tab. 62. MODECFG_2_1 register bit description .......... 55
Tab. 63. SW2 default output voltage for mode
setting 2 ...........................................................55
Tab. 64. MODECFG_2_2 register bit description .......... 56
Tab. 65. LDO1 default output voltage for mode
setting 2 ...........................................................56
Tab. 66. MODECFG_2_3 register bit description .......... 56
Tab. 67. LDO2 default output voltage for mode
setting 2 ...........................................................57
Tab. 68. MODECFG_3_0 register bit description .......... 57
Tab. 69. SW1 output voltage for mode setting 3 ........... 58
Tab. 70. MODECFG_3_1 register bit description .......... 58
Tab. 71. SW2 default output voltage for mode
setting 3 ...........................................................59
Tab. 72. MODECFG_3_2 register bit description .......... 59
Tab. 73. LDO1 default output voltage for mode
setting 3 ...........................................................59
Tab. 74. MODECFG_3_3 register bit description .......... 60
Tab. 75. LDO2 default output voltage for mode
setting 3 ...........................................................60
Tab. 76. RESET monitor register bit description ........... 61
Tab. 77. Limiting values ................................................ 62
Tab. 78. Limiting values ................................................ 62
Tab. 79. Recommended operating conditions ...............62
Tab. 80. EC table for Top level ..................................... 63
Tab. 81. EC table for Linear Charger ............................66
Tab. 82. EC table for BUCK1 (SW1) .............................69
Tab. 83. EC table for BUCK2 (SW2)  ...........................71
Tab. 84. EC table for LDO1 .......................................... 72
Tab. 85. EC table for LDO2 .......................................... 73
Tab. 86. EC table for I2C and Logic ..............................74
Tab. 87. Dimensions and quantities .............................. 79
Tab. 88. Carrier tape dimensions ..................................79
Tab. 89. Dimensions and quantities .............................. 80
Tab. 90. Carrier tape dimensions ..................................80
Tab. 91. Revision history ...............................................81
PCA9420
All information provided in this document is subject to legal disclaimers.
© 2022 NXP B.V. All rights reserved.
Product data sheet
Rev. 4.0 — 28 November 2022
84 / 87



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