PCA9420 datasheet(60/87 Pages) NXP

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

9.5.43 Mode configuration mode setting 3_3 (MODECFG_3_3, address 31h)

This register contains mode setting 3, part 3 configuration register. This is a READ AND

WRITE register.

Bit

Symbol

Default

value

Type

Function

WD_TIMER_3 [1:0]

R/W

Watchdog timer setting in mode setting 3

00: Watchdog Timer Disabled

01: Watchdog Timer = 16 s

10: Watchdog Timer = 32 s

11: Watchdog Timer = 64 s

LDO2_OUT_3_OFFSET

R/W

LDO2 output voltage offset selection in mode setting D

0: LDO2 Output Voltage = LDO2_OUT_3_LSB[4:0] + 0 V

1: LDO2 Output Voltage = LDO2_OUT_3_LSB[4:0] + 1.2 V

LDO2_OUT_3_LSB

[4:0]

01100

R/W

LDO2 default output voltage for mode setting 3 (see below)

Table 74. MODECFG_3_3 register bit description

00000=1.500 V

01001=1.725 V

10010=1.950 V

00001=1.525 V

01010=1.750 V

10011=1.975 V

00010=1.550 V

01011=1.775 V

10100=2.000 V

00011=1.575 V

01100=1.800 V

(default)

10101=2.025 V

00100=1.600 V

01101=1.825 V

10110=2.050 V

00101=1.625 V

01110=1.850 V

10111=2.075 V

00110=1.650 V

01111=1.875 V

11000=2.100 V

00111=1.675 V

10000=1.900 V

11001-11111=2.1 V

01000=1.700 V

10001=1.925 V

Table 75. LDO2 default output voltage for mode setting 3

9.5.44 RESET reason monitoring (RESET_MONITOR, address 71h)

power cycling by PMIC.

Note that SHIP_EXIT_DONE status is stored outside of the ASYS domain, so that it

survives the ship mode entry/exit. All other bits are cleared by the ship mode entry/exit,

because it cycles the power to the digital core.

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

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