PCA9420 datasheet(86/87 Pages) NXP

86 / 87 page

NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

Contents

General description ............................................ 1

Features and benefits .........................................1

Applications .........................................................2

Ordering information .......................................... 2

4.1

Ordering options ................................................ 2

Simplified block diagram ................................... 3

Pinning information ............................................ 4

6.1

Pinning ...............................................................4

6.2

Pin description ................................................... 5

System configuration diagram .......................... 7

Functional description ........................................9

8.1

Power control state diagram ..............................9

8.2

ASYS ............................................................... 10

8.3

VBAT_BKUP (back-up battery input) ............... 10

8.4

ON ....................................................................10

8.5

TS .................................................................... 11

8.6

Mode setting .................................................... 11

8.7

Mode selection by external pins

(MODESEL0, MODESEL1) ............................. 12

8.8

SYSRSTn .........................................................13

8.9

SHIP mode ...................................................... 13

8.10

Watchdog timer ................................................14

8.11

Regulators ........................................................14

8.11.1

Enable/disable and active discharge ............... 15

8.11.2

Power-good indication ..................................... 15

8.11.3

Power-up/down sequence and on-the-fly

voltage change ................................................ 15

8.11.4

BUCK1 (SW1, core buck regulator) .................17

8.11.5

BUCK2 (SW2, system buck regulator) .............17

8.11.6

LDO1 (always-on LDO) ................................... 17

8.11.7

LDO2 (system LDO) ........................................18

8.12

Linear battery charger ..................................... 18

8.12.1

Battery charging management .........................19

8.12.2

Battery temperature sensing and JEITA-

compliant charging profile ................................22

8.12.3

Battery attach detection ...................................22

8.12.4

Low-battery/dead-battery (pre-qualification)

charging ........................................................... 23

8.12.5

Constant current charging/constant voltage

charging (fast charging) and termination ......... 23

8.12.6

Charger safety timers ...................................... 23

8.12.7

Recharging .......................................................23

8.12.8

Starting a new charge cycle ............................ 23

8.13

Hardware and software reset .......................... 23

8.14

Device level protection features .......................24

I2C-bus interface and register ......................... 24

9.1

I2C target address ...........................................24

9.2

General call and device ID addresses ............. 24

9.3

9.4

9.5

9.5.1

Device information (DEV_INFO, address

00h) ..................................................................27

9.5.2

Top level interrupt status (TOP_INT,

address 01h) ....................................................27

9.5.3

Sub level interrupt_0 (SUB_INT0, address

02h) ..................................................................28

9.5.4

Sub level interrupt_0 mask (Sub_INT0_

Mask, address 03h) .........................................29

9.5.5

Sub level interrupt_1 (Sub_INT1, address

04h) ..................................................................29

9.5.6

Sub level interrupt_1 mask (Sub_INT1_

Mask, address 05h) .........................................30

9.5.7

Sub level interrupt_2 (Sub_INT2, address

06h) ..................................................................31

9.5.8

Sub level interrupt_2 mask (Sub_INT2_

Mask, address 07h) .........................................32

9.5.9

Top level control_0 (TOP_CTL0, address

09h) ..................................................................32

9.5.10

Top level control_1 (TOP_CTL1, address

0Ah) ................................................................. 33

9.5.11

Top level control_2 (TOP_CTL2, address

0Bh) ................................................................. 34

9.5.12

Top level control_3 (TOP_CTL3, address

0Ch) ................................................................. 35

9.5.13

Top level control_4 (TOP_CTL4, address

0Dh) ................................................................. 36

9.5.14

Battery charger control_0 (CHG_CTL0,

address 10h) ....................................................36

9.5.15

Battery charger control_1 (CHG_CTL1,

address 11h) ....................................................36

9.5.16

Battery charger control_2 (CHG_CTL2,

address 12h) ....................................................37

9.5.17

Battery charger control_3 (CHG_CTL3,

address 13h) ....................................................38

9.5.18

Battery charger control_4 (CHG_CTL4,

address 14h) ....................................................39

9.5.19

Battery charger control_5 (CHG_CTL5,

address 15h) ....................................................40

9.5.20

Battery charger control_6 (CHG_CTL6,

address 16h) ....................................................41

9.5.21

Battery charger control_7 (CHG_CTL7,

address 17h) ....................................................42

9.5.22

Battery charger status_0 (CHG_STATUS_

0, address 18h) ............................................... 43

9.5.23

Battery charger status_1 (CHG_STATUS_

1, address 19h) ............................................... 43

9.5.24

Battery charger status_2 (CHG_STATUS_

2, address 1Ah) ...............................................44

9.5.25

Battery charger status_3 (CHG_STATUS_

3, address 1Bh) ...............................................45

9.5.26

Regulator status (REG_STATUS, address

20h) ..................................................................45

9.5.27

Active Discharge Regulator control (ACT_

DISCHARGE_CNTL, address 21h) ................. 46

9.5.28

Mode configuration mode setting 0_0

(MODECFG_0_0, address 22h) ...................... 47

9.5.29

Mode configuration mode setting 0_1

(MODECFG_0_1, address 23h) ...................... 48

9.5.30

Mode configuration mode setting 0_2

(MODECFG_0_2, address 24h) ...................... 49

PCA9420

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Product data sheet

Rev. 4.0 — 28 November 2022

86 / 87

PCA9420 Datasheet(PDF) 86 Page - NXP Semiconductors

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