PCA9420 datasheet(24/87 Pages) NXP

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

8.14 Device level protection features

The device contains several protection features at both the complete IC level and have

a reaction at each of the functional blocks (linear charger, DC-DC converters, LDOs).

There are additional protection mechanisms at the functional block level, but those are

already documented on its respective functional description section.

Protection reaction

Condition

Triggering point

Overall Device state

Linear charger

DC-DC converters

LDOs

VIN undervoltage

VIN < VIN_UVLO

Operational

Disabled

Remain operational

although might deliver a

reduced output voltage

(due to low VIN)

Remain operational

although might deliver a

reduced output voltage

(due to low VIN)

Maintained. Interrupt

triggered, status

reported.

VIN overcurrent

(ILIM)

VIN current is > VIN_

ILIM

Reset if ASYS < ASYS_

UVLO; otherwise

Operational

RESET state if ASYS <

VBAT_Vheadroom; otherwise

operational

Remain operational up

to the point of ASYS_

UVLO

Remain operational up

to the point of ASYS_

UVLO

Maintained unless reset

happened; Interrupt and

status reported.

ASYS undervoltage ASYS < ASYS_UVLO

RESET

RESET state

Turned off, restarted

in initial state when

condition goes away

Turned off, restarted

in initial state when

condition goes away

Reset to their default

value

IC overtemperature Chip temperature >

THM_REG

RESET

RESET state

Turned off, restarted

in initial state when

condition goes away

Turned off , restarted

in initial state when

condition goes away

Reset to their default

value. Status available

in register 0x71.

Watchdog timer

expiration

Watchdog counter >

WD_Timer_0 setting

Operational

Depends on the value of

nEN_CHG_IN_WATCHDOG

bit

Set to mode 0

Maintained. Status

available in register

0x71.

Table 6. Device level protection features

9 I2C-bus interface and register

The PCA9420 implements an I2C-bus target interface to communicate with the host

system. The interface supports Fast Mode plus Fm+ with up to 1 Mbit/s. A detailed

description of the I2C-bus specification is given in UM10204, Rev. 06, 4 April 2014 ,“ I2C-

bus specification and user manual”.

Features such as clock-stretching and 10-bit target address are not supported; general

call is supported by default but can be disabled via metal option. Auto increment with

address wrap-around is supported as well.

9.1 I2C target address

Following a START condition, the bus controller must send the target address followed by

a read or write operation. The target address of the PCA9420 is shown below:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0/1

Fixed

MTP option

Fixed

R/W

Table 7. I2C target address

Bit 4 should be reserved as MTP option, with its default value set as “0” but can be

trimmed to “1” when needed.

9.2 General call and device ID addresses

The device implements two different addresses for general call and device ID.

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

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