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PCA9420 Datasheet(PDF) 27 Page - NXP Semiconductors |
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PCA9420 Datasheet(HTML) 27 Page - NXP Semiconductors |
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27 / 87 page ![]() NXP Semiconductors PCA9420 Power management IC for low-power microcontroller applications Address (Hex) Register Name Description Type Reset Value (Binary) 71 Reset monitor Reset reason monitor R RO R/W 1000 0000 Table 8. Register map...continued 9.5 Register description 9.5.1 Device information (DEV_INFO, address 00h) The device identification code stores a unique identifier for each version and/or revision of device, so that the connected MCU recognizes it automatically. This is a READ ONLY register. Bit Symbol Default value Type Function 7 DEV_ID [4] 0 R 6 DEV_ID [3] 0 R 5 DEV_ID [2] 0 R 4 DEV_ID [1] 0 R 3 DEV_ID [0] 0 R Device ID 2 DEV_REV [2] 0 R 1 DEV_REV [1] 0 R 0 DEV_REV [0] 1 R Device revision Table 9. DEV_INFO register bit description 9.5.2 Top level interrupt status (TOP_INT, address 01h) The top-level interrupt register contains flags indicating various top level interrupt events as indicated below. An event will be latched and only its first occurrence triggers the interrupt signal INTB (if it is not being masked). Reoccurring events will not change the flag's status or trigger an additional interrupt. If multiple interrupt events happen, its corresponding interrupt bits in the related registers will be “triggered”, however, the INTB signal will be only triggered upon the first interrupt event. The interrupt event reporting on the device is structured in a two-layer configuration. The interrupt events are grouped as (1) system level; (2) charger block; (3) buck regulator block; (4) LDO block. When any interrupt event is triggered, based on which mode it falls into, the related bit for that mode in TOP_INT flags “1”. Any of the related bits in TOP_INT will only change back to 0 when all the interrupt events in its affiliated mode have been cleared. This is READ Only register. Bit Symbol Default value Type Function 7 RSVD 0 R Reserved bit 6 RSVD 0 R Reserved bit 5 RSVD 0 R Reserved bit Table 10. TOP_INT register bit description PCA9420 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 28 November 2022 27 / 87 |
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