PCA9420 datasheet(13/87 Pages) NXP

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

MODESEL1 pin voltage level

MODESEL0 pin voltage level

All Settings from

HIGH (1)

Mode Setting 3

Table 4. Mode selection by external pins (MODESEL0, MODESEL1)...continued

8.8 SYSRSTn

The SYSRSTn is implemented as an open-drain output signal. It is used as an output of

“power-good” indication as well as to reset the microcontroller system.

The SYSRSTn signal is held from high to low under one of following conditions:

1. When any of the enabled voltage rail output voltage drops below 90 % (typ) of its

target value.

2. When any of the enabled voltage rail output voltage goes above 110 % (typ) of its

target value

If any of the voltage rail is disabled by the user (by setting the corresponding enable

bit in I2C register in each mode setting, i.e., LDO1_EN_x, LDO2_EN_x, SW1_EN_x,

SW2_EN_x), the SYSRSTn signal should NOT assert (stays high) under such scenario.

This also applies during the power-up/power-down sequence events, i.e., during power-

up or power-down event, the SYSRSTn signal should assert when any of the enabled rail

has not reaches the 90 % to 110 % of its target value. In other words, the SYSRSTn = 0

(low) needs to remain at such state until all enabled rails reach 90 % of the target values.

Once the condition that caused the SYSRSTn signal to go low is removed, then the

SYSRSTn should refresh accordingly.

Meanwhile, during the voltage change on-the-fly, this could be caused by:

1. Mode setting remains the same, but the user chooses to change one or some of the

enabled output rail voltage by programming its output voltage I2C register setting

2. Mode setting changes by setting different values on MODESEL0/MODESEL1 pins or

MODE0_I2C/MODE1_I2C bits, and it causes one or some of the output rail voltage

change

In such case, the SYSRSTn signal does NOT assert when any of the enabled voltage

rail output voltage is in the middle of the transition from initial output voltage level to

target level.

8.9 SHIP mode

PCA9420 features a “SHIP mode”, in which the chip provides the lowest quiescent

consumption.

To enter the SHIP mode, set the bit of SHIP_EN_x (x can be 0, 1, 2 or 3) in each Mode

of any operation under any mode setting. It means that the SHIP mode has a higher

priority over any conditions and operations.

Upon request to enter the ship mode while the device is running in active mode, a power-

down sequence should take place first and then enter the ship mode.

Once the device

enters ship mode, all the I2C register values are reset to their default setting.

To exit ship mode, one of the following conditions must be satisfied:

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

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