PCA9420 datasheet(33/87 Pages) NXP

33 / 87 page

NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

Bit

Symbol

Default value Type

Function

7:5

VIN_ILIM_SEL

[2:0]

010

R/W

VIN input current limit selection: (min/typ/max)

000: 74 mA/85 mA/98 mA, (another default setting by MTP)

001: 222 mA/255 mA/293 mA

010: 370 mA/425 mA/489 mA (default setting)

011: 517 mA/595 mA/684 mA

100: 665 mA/765 mA/880 mA

101: 813 mA/935 mA/1075 mA

110: 961 mA/1105 mA/1271 mA

111: Input current limit disabled

Note: VIN_ILIM_SEL [1] is the only bit that is MTP configurable

OPERATION_SEL_

FROM_SHIPMODE

R/W

Ship mode wakeup configuration setting

0: upon VIN plug in, the chip will enable the battery charging

process, AND start the power-up sequence for LDO1/LDO2/

SW1/SW2 per the setting

1: upon VIN plug in, the chip will enable the charging process,

LDO1/LDO2/SW1/SW2 remain in shutdown mode and the chip

will only enable the power-up sequence upon ON pin falling

edge

Note: This bit is MTP configurable

PWR_DN_EN[1]

R/W

Power-down Sequence Enable

0: Do not start power-down sequence

1: Start power-down sequence

nEN_CHG_IN_

WATCHDOG

R/W

Configure operations in a programmed watchdog timer expired

0: When the programmed watchdog timer expires, the following

operations take place.

• SYSRSTn signal asserts (high to low)

• Charging is continued

• LDO1/LDO2/SW1/SW2 enters the mode 0 setting

1: When the programmed watchdog timer expires, the following

operations take place.

• SYSRSTn signal asserts (high to low)

• Charging is disabled

• LDO1/LDO2/SW1/SW2 enters the mode 0 setting

RSVD

R/W

Reserved bit

PGood_EN

R/W

LDO1, LDO2, SW1, SW2 Output Voltage Status Indication

0: Output voltage power-good comparators are disabled.

This will also set “VOUTSW1 _OK”, “VOUTSW2 _OK”,

“VOUTLDO1_OK” and “VOUTLDO2 _OK” bits to 0

1: Output voltage power-good comparators are enabled

Table 17. TOP_CNTL0 register bit description

[1]

A valid VIN does not generate the initial power-up sequence if all power rails have been turned off by setting PWR_DN_EN to 1. The use of PWR_DN_EN

bit is prohibited to be used in any application that requires power-up sequence by both VIN and ON key.

The use of SHIP_EN_x (x can be 0, 1, 2 &3) is recommended for the application.

9.5.10 Top level control_1 (TOP_CTL1, address 0Ah)

This register contains various configuration bits for top level related functions, part 1. This

is a READ AND WRITE register.

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.0 — 28 November 2022

33 / 87

PCA9420 Datasheet(PDF) 33 Page - NXP Semiconductors

PCA9420 Datasheet(HTML) 33 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL