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PCA9420 Datasheet(PDF) 31 Page - NXP Semiconductors |
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PCA9420 Datasheet(HTML) 31 Page - NXP Semiconductors |
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31 / 87 page ![]() NXP Semiconductors PCA9420 Power management IC for low-power microcontroller applications Bit Symbol Default value Type Function 6 ICHG_DEAD_TIMER_INT_MASK 1 R/W Dead charge timer Interrupt Mask bit 0: Not Masked 1: Masked 5 VIN_ILIM_MASK 1 R/W Input Current Limit Interrupt Mask bit 0: Not Masked 1: Masked 4 ICHG_FAST_TIMER_MASK 1 R/W Fast Charging Timer Expiration Interrupt Mask bit 0: Not Masked 1: Masked 3 ICHG_PREQ_TIMER_MASK 1 R/W Pre-qual Charging Timer Expiration Interrupt Mask bit 0: Not Masked 1: Masked 2 BATTERY_DETECTION_MASK 1 R/W Battery presence Interrupt Mask bit 0: Not Masked 1: Masked 1 VBAT_MASK 1 R/W Battery Interrupt Mask bit 0: Not Masked 1: Masked 0 CHG_OK_MASK 1 R/W Charger Interrupt Mask bit 0: Not Masked 1: Masked Table 14. Sub_INT1_Mask register bit description...continued 9.5.7 Sub level interrupt_2 (Sub_INT2, address 06h) The sub-level interrupt register contains flags indicating the second-tier interrupt event. For this register, it contains LDO1/LDO2, SW1/SW2 related interrupt events reflected on the SW_INT and LDO_INT bits on the TOP_INT register as long as they are unmasked on the Sub_INT2_Mask register. This is WRITE AND CLEAR register. Bit Symbol Default value Type Function 7 RSVD 0 W/C Reserved bit 6 RSVD 0 W/C Reserved bit 5 RSVD 0 W/C Reserved bit 4 RSVD 0 W/C Reserved bit 3 VOUTSW1 0 W/C SW1 Output Voltage Interrupt 0: The VOUTSW1_OK bit has not changed since the last time this bit was cleared. 1: The VOUTSW1_OK bit has changed since the last time this bit was cleared. Table 15. Sub_INT2 register bit description PCA9420 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 4.0 — 28 November 2022 31 / 87 |
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