R2000 datasheet(36/75 Pages) ETC

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Indy® R2000 Electrical, Mechanical, & Thermal Specification

Addr.

Name

R/W

Bit

Description

Reset

Type

Comment

0c0

TX_ENABLE

R/W

7:6

5:4

3:2

IQ correction Enable

Bypass of Hilbert filter

Hilbert filter order select

Not used

IQ input select

TX mode (Q)

TX mode (I)

SSB Enable

Not used

h0000

Setup register for the TX

data path.

If IQ correction is enabled

the latency of the data

path is increased by one

TX clock cycle.

The Hilbert filter can be

switched between two

orders:

= 10th order

= 22nd order

The IQ correction input

select can be set to the

following values:

11, 10 = Control output

01 = Bypass interpolation

filter

00 = Enable interpolation

filter

TX mode can be set to the

following values:

11 = Use predistortion

10 = Use output of power

scaler

01 = Use Hilbert

transformer

00 = Use Hilbert

transformer and

CORDIC.

0c1

TX_COEFF1

R/W

11:0

Hilbert coefficient 1

h0009

s1.10

Used for 22nd order only,

must be set to zero for the

10th order filter.

0c2

TX_COEFF3

R/W

11:0

Hilbert coefficient 3

h0017

s1.10

Used for 22nd order only,

must be set to zero for the

10th order filter.

0c3

TX_COEFF5

R/W

11:0

Hilbert coefficient 5

h0031

s1.10

Used for 22nd order only,

must be set to zero for the

10th order filter.

0c4

TX_COEFF7

R/W

11:0

Hilbert coefficient 7

h005f

s1.10

0c5

TX_COEFF9

R/W

11:0

Hilbert coefficient 9

h00c2

s1.10

0c6

TX_COEFF11

R/W

11:0

Hilbert coefficient 11

h0284

s1.10

0c7

TX_FREQ1

R/W

2:0

CORDIC offset

h0000

u1.18

Frequency offset value, bit

18:16. Specified as a

fraction of 2π radians per

TX clock cycle.

0c8

TX_FREQ2

R/W

15:0

CORDIC offset

h0000

Frequency offset value, bit

15:0. Specified as a

fraction of 2π radians per

TX clock cycle.

0c9

GEN_RATE

R/W

9:0

TX clock cycle duration

h0078

Specifies the TX clock

cycle in 48 MHz clock

cycles.

0ca

TX_TO

R/W

15:0

Final ramp-down, hold time

h0000

Time to wait after the final

ramp-down before the PA

is disabled. Specified in

48 MHz clock cycles.

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