PD6710 datasheet(82/138 Pages) INTEL

82 / 138 page

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers

Datasheet

10.7.5

External Data (PD6722 only, Socket A, Index 6Fh)

Bits 7:0 — External Data

This register is updated and accessed according to the setting of bits 3 and 4 of the Socket B

Extension Control 2 register (Index 6Fh, Extended Index 0Bh).

Note:

For software compatibility of external data access accross the PC Card (PCMCIA) controller

product line, the Socket B External Data register should only be used as a read port and not as a

write port. Also for compatibility, only the lower nibble of External Data should be accessed and

the upper nibble should be ignored. For software compatibility with VS1# and VS2# detection

software, when Socket B is used as a read port, socket VS1# and VS2# signals should be connected

to the external read buffer as shown in Figure 15 on page 96.

Refer to “Using GPSTB Pins for External Port Control (PD6722 only)” on page 91 for more

information on the use of the External Data register, and “VS1# and VS2# Voltage Detection” on

page 95 for more information on VS1# and VS2# detection.

Index: 6Fh only

Extended Index: 0Ah

Bit 7Bit 6Bit 5

Bit 4

Bit 3Bit 2Bit 1Bit 0

External Data

3 or

B_VS2# Input

External Data

2 or

B_VS1# Input

External Data

1 or

A_VS2# Input

External Data

0 or

A_VS1# Input

RW:0

R:0

Table 16. Functions of Socket B External Data Register (PD6722 only)

Socket B Extension Control 2

Function of Socket B External Data Register

Bit 4: GPSTB

on IOW*

Bit 3: GPSTB

on IOR*

Bits 7:4 — scratchpad

Bits 3:2 — Socket B VS2# and VS1# levels (PD6722 only)

Bits 1:0 — Socket A VS2# and VS1# levels

External read port: B_GPSTB is a read buffer enable for external data on

SD[15:8].

External write port: B_GPSTB is a write latch enable for SD[15:8] to get

latched to an external register. Reads of Socket B External Data register

produce the value written to the latch.

Reserved

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