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PD6710 Datasheet(PDF) 94 Page - Intel Corporation |
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PD6710 Datasheet(HTML) 94 Page - Intel Corporation |
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94 / 138 page  PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers 94 Datasheet In this mode, Extension Control 2 register bit 3 is set to ‘1’, enabling the respective GPSTB pin to function as a read strobe. Reads from the corresponding extended index 0Ah cause GPSTB to go active (default active level is low) for the duration of the system’s IOR* pulse. Note: Data is still written to the shadowed External Data register on writes to Extended Index 0Ah but is not visible. 13.3 GPSTB in Suspend Mode GPSTB read and write strobes operate while the device is in suspend mode, but they are not allowed when the device is in hardware-assisted ‘Super-Suspend’ mode (AEN held high while in Suspend mode). A clock to the PD6722 is not required for the external signal at GPSTB to occur, but shadowing of write values in the internal register at Extended Index 0Ah requires that the PD67XX is not in Suspend mode so there is an active internal clock for register writes. |
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