RT600 datasheet(20/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.1 — 7 July 2023

20 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

PIO0_13/

CH1B

G16

Z I/O;

PIO0_13/CH1B — General-purpose digital input/output pin.

Analog input 1B. Can optionally be paired with CH1A for

differential input on ADC channel 1.

I/O 1

FC1_SSEL3 — Flexcomm 1: SPI slave select 3.

SCT0_GPI3 — Pin input 3 to SCTimer/PWM.

SCT0_OUT3 — SCTimer/PWM output 3.

CTIMER0_MAT1 — 32-bit CTimer0 match output 1.

R — Reserved.

I/O 8

SEC_PIO0_13 — Secure GPIO pin.

PIO0_14

B17

Z I/O 0

PIO0_14 — General-purpose digital input/output pin.

I/O 1

FC2_SCK — Flexcomm 1: USART, SPI, or I2S clock.

SCT0_GPI0 — Pin input 0 to SCTimer/PWM.

SCT0_OUT0 — SCTimer/PWM output 0.

CTIMER2_MAT0 — 32-bit CTimer2 match output 0.

I2S_BRIDGE_CLK_IN — Allows I2S bypass by re-routing

this function to a pin that includes the

I2S_BRIDGE_CLK_OUT function.

R — Reserved.

I/O 8

SEC_PIO0_14 — Secure GPIO pin.

PIO0_15

A16

Z I/O 0

PIO0_15 — General-purpose digital input/output pin.

I/O 1

FC2_TXD_SCL_MISO_WS — Flexcomm 2: USART

transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S

word select/frame.

SCT0_GPI1 — Pin input 1 to SCTimer/PWM.

SCT0_OUT1 — SCTimer/PWM output 1.

CTIMER2_MAT1 — 32-bit CTimer2 match output 1.

I2S_BRIDGE_WS_IN — Allows I2S bypass by re-routing this

function to a pin that includes the I2S_BRIDGE_WS_OUT

function.

R — Reserved.

I/O 8

SEC_PIO0_15 — Secure GPIO pin.

Table 4.

Pin description …continued

Symbol

Description

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