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RT600 Datasheet(PDF) 70 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 70 Page - NXP Semiconductors |
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70 / 171 page  RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2023. All rights reserved. Product data sheet Rev. 2.1 — 7 July 2023 70 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs 10.13.5 Safety The RT600 includes a Windowed WatchDog Timer (WWDT), which can be enabled by software after reset. Once enabled, the WWDT remains locked and cannot be modified in any way until a reset occurs. Fig 8. RT600 clock generation (continued) 191220 Timer function clocks: Other (analog, audio, misc.): CLKOUT 1 select CLKOUTSEL1[2:0] CLKOUTDIV CLKOUT Divider audio_pll_clk 32k_clk main_pll_clk aux0_pll_clk dsp_pll_clk aux1_pll_clk "none" 011 001 010 000 100 101 110 111 CLKOUT dsp_main_clk clk_in 1m_lposc 48/60m_irc 16m_irc main_clk 011 001 010 000 100 110 CLKOUT 0 select CLKOUTSEL0[2:0] ADC0FCLKDIV ADC Clock Divider to ADC fclk aux0_pll_clk ADC clock select 1 ADC0FCLKSEL1[2:0] main_pll_clk aux1_pll_clk 101 001 011 000 111 "none" ADC clock select 0 ADC0FCLKSEL0[2:0] clk_in 1m_lposc 48/60m_irc 16m_irc 011 001 010 000 111 "none" ACMP0FCLKDIV ACMP Clock Divider to ACMP fclk 48/60m_irc ACMP clock select ACMP0FCLKSEL[2:0] 16m_irc aux0_pll_clk aux1_pll_clk main clk 011 001 010 000 100 111 "none" DMIC0FCLKDIV DMIC Clock Divider to D-Mic subsystem DMIC Clock Select DMIC0FCLKSEL[2:0] 48/60m_irc 16m_irc audio_pll_clk 1m_lposc mclk_in 011 001 010 000 100 101 111 "none" 32k_wake_clk 111 001 010 000 OS Timer Clock Select OSEVENTTFCLKSEL[2:0] ostimer_clk 32k_clk 1m_lposc hclk "none" TIMER n clock select CT32BITnFCLKSEL[2:0] 16m_irc 48/60m_irc audio_pll_clk main clk mclk_in "none" function clock of CTIMER n (CTIMERs 0 through 4) 011 001 010 000 100 111 SCTimer/PWM clock select SCTFCLKSEL[2:0] SCTFCLKDIV SCTimer/PWM Clock Divider to SCTimer/PWM input clock 7 main_pll_clk aux0_pll_clk 48/60m_irc main clk aux1_pll_clk audio_pll_clk "none" 011 001 010 000 100 101 111 WDT0 Clock Select WDT0FCLKSEL[2:0] to WDT0 fclk 1m_lposc "none" 111 000 WDT1 Clock Select WDT1FCLKSEL[2:0] to WDT1 fclk 1m_lposc "none" 111 000 Utick Timer Clock Select UTICKFCLKSEL[2:0] to UTICK fclk 1m_lposc "none" 111 000 |
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